Datasheet

Table 24-22. Enhanced Receive Descriptor 0 (RDES0) (continued)
DescriptionBit
FT: Frame Type
When set, this bit indicates that the Receive Frame is an Ethernet-type frame (the LT field is greater than or equal
to 1,536). When this bit is reset, it indicates that the received frame is an IEEE 802.3 frame. This bit is not valid
for Runt frames less than 14 bytes.
5
RWT: Receive Watchdog Timeout
When set, this bit indicates that the Receive Watchdog Timer has expired while receiving the current frame and
the current frame is truncated after the Watchdog Timeout.
4
RE: Receive Error
When set, this bit indicates that an error occurred during frame reception.
3
DE: Dribble Bit Error
When set, this bit indicates that the received frame has a non-integer multiple of bytes (odd nibbles). This bit is
valid only in MII Mode.
2
CE: CRC Error
When set this bit indicates that a Cyclic Redundancy Check (CRC) Error occurred on the received frame. This
field is valid only when the Last Descriptor bit (RDES0[8]) is set.
1
Extended Status Available/RX MAC Address
This bit, when set, indicates that the extended status is available in descriptor word 4 (RDES4). This is valid only
when the Last Descriptor bit (RDES0[8]) is set. This bit is invalid when Bit 30 is set.
0
Table 24-23. Enhanced Receive Descriptor 1 (RDES1)
DescriptionBit
Disable Interrupt on Completion
When set this bit prevents the setting of the bit Receive Interrupt (RI) bit in the EMACDMARIS register and
prevents the receive interrupt from being asserted.
31
Reserved30:29
RBS2: Receive Buffer 2 Size
These bits indicate the second data buffer size. The buffer size must be a multiple of 4, even if the value of
RDES3 (buffer2 address pointer) is not aligned to the bus width. If the buffer size is not an appropriate
multiple of 4, the resulting behavior is undefined. This field is not valid if RCH bit (RDES1[14]) is set.
28:16
RER: Receive End of Ring
When set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns to the base
address of the list, creating a Descriptor Ring.
15
RCH: Second Address Chained
When set, this bit indicates that the second address in the descriptor is the Next Descriptor address rather
than the second buffer address. When this bit is set, RBS2 (RDES1[28:16]) is a don’t care value. RDES1[15]
takes precedence over RDES1[14].
14
Reserved13
RBS1: Receive Buffer 1 Size
Indicates the first data buffer size in bytes. The buffer size must be a multiple of 4 even if the value of RDES2
(buffer 1 address pointer) is not aligned. When the buffer size is not a multiple of 4, the resulting behavior
is undefined. If this field is 0, the DMA ignores this buffer and uses Buffer 2 or the next descriptor depending
on the value of RCH (Bit 14).
12:0
1621December 13, 2013
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TM4C129XNCZAD Microcontroller