Datasheet

Figure 24-10. Enhanced Receive Descriptor Structure
31 0723 15
Status [30:0]
Byte Count Buffer 1
[12:0]
Byte Count
Buffer2 [28:16]
RDES0
RDES1
RDES2
RDES3
Buffer1 Address [31:0]
Buffer2 Address [31:0]/Next Descriptor Address [31:0]
OWN
Receive Timestamp High [31:0]
Receive Timestamp Low [31:0]
Reserved
Extended Status [31:0]
CTRL
CTRL
[15:14]
RDES4
RDES5
RDES6
RDES7
Reserved
Reserved
[30:29]
The following tables define the Enhanced Receive Descriptors.
Table 24-22. Enhanced Receive Descriptor 0 (RDES0)
DescriptionBit
OWN: Own Bit
When set, this bit indicates that the descriptor is owned by the DMA. When this bit is reset, it indicates that the
descriptor is owned by the Host. The DMA clears this bit either when it completes the frame reception or when
the buffers that are associated with this descriptor are full.
31
AFM: Destination Address Filter Fail
When set, this bit indicates a frame failed in the DA filter in the MAC.
30
FL: Frame Length
These bits indicate the byte length of the received frame that was transferred to the system memory. This field
is valid when the Last Descriptor (RDES0[8]) is set and either the Descriptor Error (RDES0[14]) or the Overflow
Error bit (RDES0[11]) is clear.
When the Last Descriptor bit is not set, this field indicates the accumulated number of bytes that have been
transferred for the current frame. The inclusion of CRC length in the frame length depends on the settings of
CRC configuration bits, ACS and CST in the EMACCFG register.
29:16
1619December 13, 2013
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TM4C129XNCZAD Microcontroller