Datasheet

Table 24-19. Enhanced Transmit Descriptor 3 (TDES3)
DescriptionBit
Buffer 2 Address Pointer (Next Descriptor Address)
Indicates the physical address of Buffer 2 when a descriptor ring structure is used. If the Second Address
Chained (TDES0[20]) bit is set, this address contains the pointer to the physical memory where the Next
Descriptor is present. The buffer address pointer must be aligned to the bus width only when TDES0[20] is
set.
Note that the buffers are stored in SRAM.
31:0
Table 24-20. Enhanced Transmit Descriptor 6 (TDES6)
DescriptionBit
TTSL: Transmit Frame Timestamp Low
This field is updated by DMA with the least significant 32 bits of the timestamp captured for the corresponding
transmit frame. This field has the timestamp only if the Last Segment bit (LS), TDES0[29], in the descriptor
is set and Timestamp status (TTSS) bit, TDES0[17], is set.
31:0
Table 24-21. Enhanced Transmit Descriptor 7 (TDES7)
DescriptionBit
TTSH: Transmit Frame Timestamp High
This field is updated by DMA with the most significant 32 bits of the timestamp captured for the corresponding
receive frame. This field has the timestamp only if the Last Segment bit (LS), TDES0[29], in the descriptor
is set and Timestamp status (TTSS) bit , TDES0[17], is set.
31:0
Enhanced Receive Descriptor
Figure 24-10 on page 1619 shows the enhanced receive descriptor. This descriptor is used when
Advanced Timestamp or the Checksum Offload Engine is enabled.
Note: When Advanced Timestamp feature is enabled, software should set the ATDS bit of the
Ethernet MAC DMA Bus Mode (EMACDMABUSMOD) register, offset 0xC00, so that the
DMA operates with extended descriptor size. When this bit is clear, the RDES4-RDES7
descriptor space is not valid.
December 13, 20131618
Texas Instruments-Advance Information
Ethernet Controller