Datasheet

Table 24-16. Enhanced Transmit Descriptor 0 (TDES0) (continued)
DescriptionBit
ED: Excessive Deferral
When set, this bit indicates that the transmission has ended because of excessive deferral of over 24,288 bit
times (155,680 bits times when Jumbo Frame is enabled). This bit is dependent on the Deferral Check (DC) bit
being enabled in the EMACCFG register.
2
UF: Underflow Error
When set, this bit indicates that the MAC aborted the frame because the data arrived late from system memory.
Underflow Error indicates that the DMA encountered an empty Transmit Buffer while transmitting the frame. The
transmission process enters the suspended state and sets both Transmit Underflow (UNF) and Transmit Interrupt
(TI) bit in the EMACDMARIS register.
1
DB: Deferred Bit
This bit indicates the deferral mechanism is active and that the transmit state machine sends a JAM pattern to
defer reception when it senses a carrier before a normal transmission is scheduled.
0
Table 24-17. Enhanced Transmit Descriptor 1 (TDES1)
DescriptionBit
SAIC: SA Insertion Control
These bits request the MAC to add or replace the Source Address field in the Ethernet frame with the value
given in the MAC Address 0 register. If the Source Address field is modified in a frame, the MAC automatically
recalculates and replaces the CRC bytes.
The Bit 31 specifies the MAC Address Register (1 or 0) value that is used for Source Address insertion or
replacement. The following list describes the values of Bits[30:29]:
■ 0x0= Do not include the source address.
■ 0x1= Insert the source address. For reliable transmission, the application must provide frames without
source addresses.
■ 0x2= Replace the source address. For reliable transmission, the application must provide frames with
source addresses.
■ 0x3= Reserved
These bits are valid when the First Segment control bit (TDES0[28]) is set.
31:29
TBS2: Transmit Buffer 2 Size
This field indicates the second data buffer size in bytes. This field is not valid if TDES0[20] is set.
28:16
Reserved15:13
TBS1: Transmit Buffer 1 Size
These bits indicate the first data buffer byte size, in bytes. If this field is 0, the DMA ignores this buffer and
uses Buffer 2 or the next descriptor, depending on the value of TCH (TDES0[20]).
12:0
Table 24-18. Enhanced Transmit Descriptor 2 (TDES2)
DescriptionBit
Buffer 1 Address Pointer
These bits indicate the physical address of Buffer 1. There is no limitation on the buffer address
alignment. Note that the buffers are stored in SRAM.
31:0
1617December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller