Datasheet

Table 24-7. Receive Descriptor 0 (RDES0) (continued)
DescriptionBit
RX MAC Address or Payload Checksum Error
When set, this bit indicates that the Ethernet MAC Address n (EMACADDRXH/L) registers value matched the
frame's DA field. When reset, this bit indicates that the Ethernet MAC Address 0 H/L (EMACADDR0H/L) register
value matched the DA field. This bit is invalid when Bit 30 is set.
If the Full Checksum Offload Engine is enabled, this bit, when set, indicates that the received number of payload
bytes does not match the value indicated in the Length field of the encapsulated IPv4 or IPv6 datagram in the
received Ethernet frame
0
Table Table 24-8 on page 1611 shows the frame information conveyed in bits 7, 5, and 0 of RDES0
when the Checksum Offload Engine is enabled and disabled through the IPC bit in the EMACCFG
register.
Table 24-8. RDES0 Checksum Offload bits
Frame StatusIPC bit value
in EMACCFG
register
Bit 0: Payload
Checksum
Error
Bit 7: IPC
Checksum
Error
Bit 5:
Frame
Type
IEEE 802.3 Type frame (Length field value is less than 1,536).
This status definition is valid even when the Checksum Offload
engine is disabled.
X000
IPv4/IPv6 Type frame in which no checksum error is detected.0001
The frame is an IEEE 802.3 Type frame (Length field value is
greater than or equal to 1,536).
1001
IPv4/IPv6 Type frame with a payload checksum error detected1101
IPv4/IPv6 Type frame with both IP header and payload
checksum errors detected
1111
IPv4/IPv6 Type frame with no IP header checksum error and
the payload check bypassed, due to an unsupported payload
1100
A Type frame that is neither IPv4 or IPv6 (the Checksum Offload
engine bypasses checksum completely.)
1110
ReservedX010
RDES1 contains the buffer sizes and other bits that control the descriptor chain or ring.
Table 24-9. Receive Descriptor 1 (RDES1)
DescriptionBit
Disable Interrupt on Completion
When set this bit prevents the setting of the bit Receive Interrupt (RI) bit in the EMACDMARIS register
and prevents the receive interrupt from being asserted.
31
Reserved30:26
RER: Receive End of Ring
When set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns to the
base address of the list, creating a Descriptor Ring.
25
RCH: Second Address Chained
When set, this bit indicates that the second address in the descriptor is the Next Descriptor address
rather than the second buffer address. When RDES1[24] is set, RBS2 (RDES1[21-11]) is a don’t care
value. RDES1[25] takes precedence over RDES1[24].
24
Reserved23:22
1611December 13, 2013
Texas Instruments-Advance Information
Tiva
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TM4C129XNCZAD Microcontroller