Datasheet

TDES3 contains the address pointer either to the second buffer of the descriptor or the next descriptor.
Table 24-6. Transmit Descriptor 3 (TDES3)
DescriptionBit
Buffer 2 Address Pointer (Next Descriptor Address)
Indicates the physical address of Buffer 2 when a descriptor ring structure is used. If the Second Address
Chained (TDES1[24]) bit is set, this address contains the pointer to the physical memory where the Next
Descriptor is present. The buffer address pointer must be aligned to the 32-bit bus when TDES1[24] is set.
31:0
24.3.4.2 Receive Descriptor
The DMA requires at least two descriptors when receiving a frame. The DMA always attempts to
acquire an extra descriptor in anticipation of an incoming frame. Before the DMA closes a descriptor,
it attempts to acquire the next descriptor even if no frames are received. In a single descriptor
(receive) system, the subsystem generates a descriptor error if the receive buffer is unable to
accommodate the incoming frame and the next descriptor is not owned by the DMA.
RDES0 contains the received frame status, the frame length, and the descriptor ownership
information.
Table 24-7. Receive Descriptor 0 (RDES0)
DescriptionBit
OWN: Own Bit
When set, this bit indicates that the descriptor is owned by the DMA. When this bit is reset, it indicates that the
descriptor is owned by the Host. The DMA clears this bit either when it completes the frame reception or when
the buffers that are associated with this descriptor are full.
31
AFM: Destination Address Filter Fail
When set, this bit indicates a frame failed in the DA filter in the MAC.
30
FL: Frame Length
These bits indicate the byte length of the received frame that was transferred to the system memory. This field
is valid when the Last Descriptor (RDES0[8]) is set and either the Descriptor Error (RDES0[14]) or the Overflow
Error bit is clear.
When the Last Descriptor bit is not set, this field indicates the accumulated number of bytes that have been
transferred for the current frame. The inclusion of CRC length in the frame length depends on the settings of
CRC configuration bits, ACS and CST in the EMACCFG register.
29:16
ES: Error Summary
Indicates the logical OR of the following bits:
■ RDES0[14]: Descriptor Error
■ RDES0[11]: Overflow Error
■ RDES0[7]: IPC Checksum (Type 2) or Giant Frame
■ RDES0[6]: Late Collision
■ RDES0[4]: Watchdog Timeout
■ RDES0[3]: Receive Error
■ RDES0[1]: CRC Error
■ RDES0[0]: Payload Checksum error
This field is valid only when the Last Descriptor (RDES0[8]) is set.
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1609December 13, 2013
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TM4C129XNCZAD Microcontroller