Datasheet

Table 24-4. Transmit Descriptor 1 (TDES1) (continued)
DescriptionBit
CIC: Checksum Insertion Control
These bits control the insertion of checksums in Ethernet frames that encapsulate TCP, UDP, or ICMP over
IPv4 or IPv6:
■ 0x0: Do nothing . Checksum Engine bypassed.
■ 0x1: Insert IPv4 header checksum. Use this value to insert IPv4 header checksum when the frame
encapsulates an IPv4 datagram.
■ 0x2: Insert TCP/UDP/ICMP checksum. The checksum is calculated over the TCP, UDP, or ICMP segment
only and the TCP, UDP, or ICMP pseudo-header checksum is assumed to be present in the corresponding
input frame's Checksum field. An IPv4 header checksum is also inserted if the encapsulated datagram
conforms to IPv4.
■ 0x3: Insert a TCP/UDP/ICMP checksum that is fully calculated in this engine. The TCP, UDP, or ICMP
pseudo-header is included in the checksum calculation, and the input frame's corresponding Checksum
field has an all-zero value. An IPv4 Header checksum is also inserted if the encapsulated datagram conforms
to IPv4.
The Checksum engine detects whether the TCP, UDP, or ICMP segment is encapsulated in IPv4 or IPv6 and
processes its data accordingly.
28:27
DC: Disable CRC
When set, the MAC does not append the Cyclic Redundancy Check (CRC) to the end of the transmitted frame.
This is valid only when the first segment (TDES1[29]) is set.
26
TER: Transmit End of Ring
When set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns to the base
address of the list, creating a descriptor ring.
25
TCH: Second Address Chained
When set, this bit indicates that the second address in the descriptor is the Next Descriptor address rather than
the second buffer address. When TDES1[24] is set, TBS2 (TDES1[21–11]) are don't care values. TDES1[25]
takes precedence over TDES1[24].
24
DP: Disable Padding
When set, the MAC does not automatically add padding to a frame shorter than 64 bytes. When this bit is reset,
the DMA automatically adds padding and CRC to a frame shorter than 64 bytes and the CRC field is added
despite the state of the DC (TDES1[26]) bit. This is valid only when the first segment (TDES1[29]) is set.
23
TTSE: Transmit Timestamp Enable
When set, this bit enables IEEE1588 hardware timestamping for the transmit frame referenced by the descriptor.
This field is valid only when the First Segment control bit (TDES1[29]) is set.
22
TBS2: Transmit Buffer 2 Size
These bits indicate the Second Data Buffer in bytes. This field is not valid if TDES1[24] is set.
21:11
TBS1: Transmit Buffer 1 Size
These bits indicate the First Data Buffer byte size. If this field is 0, the DMA ignores this buffer and uses Buffer
2 or next descriptor depending on the value of TCH (Bit 24).
10:0
TDES2 contains the address pointer to the first buffer of the descriptor.
Table 24-5. Transmit Descriptor 2 (TDES2)
DescriptionBit
Buffer 1 Address Pointer
These bits indicate the physical address of Buffer 1. There is no limitation on the buffer address
alignment.
Note: The buffer address must be in SRAM.
31:0
December 13, 20131608
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Ethernet Controller