Datasheet

Frames must be delimited by the First Segment Descriptor and the Last Segment Descriptor,
respectively. For normal descriptors, the First Descriptor bit is located at TDES1[29] and the Last
Descriptor is located at TDES1[30]. For Enhanced descriptor format, the First Segment Descriptor
bit is located in TDES0[28] and the Last Segment Descriptor bit is located in TDES0[29].
As transmission starts, the First Descriptor must have TDES1[29]/TDES0[28] set. When this occurs,
frame data transfers from the host memory buffer to the TX FIFO. Concurrently, if the current frame
has the Last Segment Descriptor (TDES1[30]/TDES0[29]) clear, the transmit process attempts to
acquire the next descriptor. The transmit process expects this descriptor to have
TDES1[29]/TDES0[28] clear. If TDES1[30]/TDES0[29] is clear, it indicates an intermediary buffer.
If TDES1[30]/TDES0[29] is set, it indicates the last buffer of the frame. After the last buffer of the
frame has been transmitted, the DMA writes back the final status information to the Transmit
Descriptor word of the descriptor that has the last segment bit set in Transmit Descriptor. At this
time, if Interrupt on Completion (IC) bit is set, the TI bit in the EMACDMARIS register is set, the
next descriptor is fetched and the process repeats.
The actual frame transmission begins after the TX FIFO has reached either the transmit threshold
as configured by the TTC bit field of the EMACDMAOPMODE register, or a full frame is contained
in the TX FIFO. To wait until there is a full frame in the TX FIFO the TSF bit in the
EMACDMAOPMODE register must be set. Descriptors are released (OWN bit in the TDES0[31]
cleared) when the DMA finishes transferring the frame.
Note: To ensure proper transmission of a frame and the next frame, the transmit descriptor that
has the Last Descriptor bit (TDES1[30]/TDES0[29]) set, must specify a non-zero buffer size.
Transmit Polling Suspended
Transmit polling can be suspended by either of the following conditions:
■ The DMA detects a descriptor owned by the CPU (TDES0[31]=0). To resume, the driver must
give descriptor ownership to the DMA and then issue a Poll Demand command.
■ A frame transmission is aborted when a transmit error because of underflow is detected. The
appropriate Transmit Descriptor 0 (TDES0) bit is set.
If the DMA goes into SUSPEND state because of the first condition, then both the Normal Interrupt
Summary (NIS) bit and the Transmit Buffer Unavailable (TU) bit are set in the EMACDMARIS
register. If the second condition occurs, the Abnormal Interrupt Summary (AIS) bit and the Transmit
Underflow (UNF) bit of the EMACDMARIS register are set and the information is written to Transmit
Descriptor 0, causing the suspension.
In both cases, the position in the Transmit list is retained . The retained position is that of the
descriptor following the last descriptor closed by the DMA. The driver must explicitly issue a Transmit
Poll Demand command after rectifying the suspension case.
24.3.3.6 DMA Receive Operation
The following section describes the receive operation process.
Default Receive Operation
The RX DMA engine's reception sequence is as follows:
1. The host sets up receive descriptors (RDES0-RDES3) and sets the OWN bit (RDES0[31]).
2. When the SR bit of the EMACDMAOPMODE register is set, the DMA enters the RUN state.
While in the RUN state, the DMA polls the Receive Descriptor list, attempting to acquire free
December 13, 20131600
Texas Instruments-Advance Information
Ethernet Controller