Datasheet

Figure 14-4. DES3DES-CFB Feedback Mode ....................................................................... 1043
Figure 14-5. DES Polling Mode ............................................................................................ 1045
Figure 14-6. DES Interrupt Service ...................................................................................... 1046
Figure 14-7. DES Context Input Event Service ...................................................................... 1047
Figure 15-1. SHA/MD5 Module Block Diagram ..................................................................... 1068
Figure 15-2. SHA/MD5 Polling Mode .................................................................................... 1079
Figure 15-3. SHA/MD5 Interrupt Subroutine ......................................................................... 1081
Figure 16-1. GPTM Module Block Diagram ........................................................................... 1103
Figure 16-2. Input Edge-Count Mode Example, Counting Down ............................................. 1111
Figure 16-3. 16-Bit Input Edge-Time Mode Example ............................................................. 1113
Figure 16-4. 16-Bit PWM Mode Example .............................................................................. 1115
Figure 16-5. CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................. 1115
Figure 16-6. CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................. 1116
Figure 16-7. CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................. 1116
Figure 16-8. Timer Daisy Chain ........................................................................................... 1117
Figure 17-1. WDT Module Block Diagram ............................................................................. 1176
Figure 18-1. Implementation of Two ADC Blocks .................................................................. 1201
Figure 18-2. ADC Module Block Diagram ............................................................................. 1202
Figure 18-3. ADC Sample Phases ....................................................................................... 1207
Figure 18-4. Doubling the ADC Sample Rate ........................................................................ 1208
Figure 18-5. Skewed Sampling ............................................................................................ 1209
Figure 18-6. Sample Averaging Example .............................................................................. 1210
Figure 18-7. ADC Input Equivalency Diagram ....................................................................... 1211
Figure 18-8. ADC Voltage Reference ................................................................................... 1212
Figure 18-9. ADC Conversion Result ................................................................................... 1213
Figure 18-10. Differential Voltage Representation ................................................................... 1215
Figure 18-11. Internal Temperature Sensor Characteristic ....................................................... 1216
Figure 18-12. Low-Band Operation (CIC=0x0 and/or CTC=0x0) .............................................. 1218
Figure 18-13. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ............................................... 1219
Figure 18-14. High-Band Operation (CIC=0x3 and/or CTC=0x3) .............................................. 1220
Figure 19-1. UART Module Block Diagram ........................................................................... 1310
Figure 19-2. UART Character Frame .................................................................................... 1313
Figure 19-3. IrDA Data Modulation ....................................................................................... 1315
Figure 20-1. QSSI Module with Advanced, Bi-SSI and Quad-SSI Support .............................. 1376
Figure 20-2. TI Synchronous Serial Frame Format (Single Transfer) ...................................... 1383
Figure 20-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................... 1384
Figure 20-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ........................ 1385
Figure 20-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 ................ 1385
Figure 20-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ....................................... 1386
Figure 20-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............. 1387
Figure 20-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ...... 1387
Figure 20-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ....................................... 1388
Figure 21-1. I
2
C Block Diagram ........................................................................................... 1425
Figure 21-2. I
2
C Bus Configuration ....................................................................................... 1427
Figure 21-3. START and STOP Conditions ........................................................................... 1428
Figure 21-4. Complete Data Transfer with a 7-Bit Address ..................................................... 1429
Figure 21-5. R/S Bit in First Byte .......................................................................................... 1429
Figure 21-6. Data Validity During Bit Transfer on the I
2
C Bus ................................................. 1429
December 13, 201316
Texas Instruments-Advance Information
Table of Contents