Datasheet

bit resides in TDES[31] for normal descriptors and TDES0[30] for alternate descriptors. The
DMA engine then returns to Step 3.
10. In the suspend state, the DMA tries to reacquire the descriptor (and thereby return to Step 3)
when it receives a transmit poll demand in the Ethernet MAC Transmit Poll Demand
(EMACTXPOLLD) register, offset 0xC04, and the Underflow Interrupt Status (UNF) bit is cleared
in the EMACDMARIS register. If the CPU stopped the DMA by clearing the ST bit of the
EMACDMAOPMODE register, the DMA enters the STOP state.
Figure 24-5 on page 1597 shows the flow for the TX DMA default operation.
December 13, 20131596
Texas Instruments-Advance Information
Ethernet Controller