Datasheet

24.3.3.4 DMA Arbiter
The arbiter inside the DMA module performs the arbitration between the Transmit and Receive
channel accesses. The DMA can be configured to arbitrate in a round-robin or fixed-priority
configuration. When the DA bit of the EMACDMABUSMOD register is clear, the DMA arbiter allocates
the data bus in the ratio set by the PR bit field of the EMACDMABUSMOD register when both the
TX and RX DMA request access at the same time. When the DA bit is set, the RX DMA always has
priority over the TX DMA for data access by default. However if the TXPR bit of the
EMACDMABUSMOD register is also set, then the TX DMA always gets priority over the RX DMA.
24.3.3.5 DMA Transmission Operation
The following sections describe the modes of the transmit operation.
TX DMA Default Operation
The TX DMA engine in default mode, operates as follows:
1. The CPU configures the transmit descriptor (TDES0-TDES3) and sets the OWN bit (TDES0[31])
after setting up the corresponding data buffers with the Ethernet frame.
2. When the ST bit of the Ethernet MAC DMA Operation Mode (EMACDMAOPMODE) register,
offset 0xC18, is set the DMA enters the RUN state.
3. While in RUN state, the DMA polls the Transmit Descriptor list for frames requiring transmission.
After polling starts, it continues in either sequential descriptor ring order or chained order. If the
DMA detects a descriptor flagged as owned by the CPU (TDES0[31]=0), or if an error condition
occurs, transmission is suspended and both the Transmit Buffer Unavailable (TU) bit and the
Normal Interrupt Summary (NIS) bit are set in the Ethernet MAC DMA Interrupt Status
(EMACDMARIS) register, offset 0xC14. The transmit engine the proceeds to Step 9.
4. If the acquired descriptor is flagged as owned by the DMA (TDES0[31]=1), the DMA decodes
the transmit data buffer address from the acquired descriptor.
5. If the acquired descriptor is flagged as owned by DMA (TDES0[31] = 1), the DMA decodes the
Transmit Data Buffer address from the acquired descriptor.
6. The DMA fetches the transmit data from system memory and transfers the data to the TX/RX
Controller for transmission.
7. If the Ethernet frame is stored over data buffers in multiple descriptors, the DMA closes the
intermediate descriptor and fetches the next descriptor. Steps 3, 4, and 5 are repeated until the
end of the Ethernet frame data is transferred to the TX/RX Controller.
8. When frame transmission is complete, if IEEE 1588 timestamping was enabled for the frame
(as indicated in the transmit status) the timestamp value is written to the transmit descriptor
(TDES2 and TDES3) that contains the end-of-frame buffer. For Enhanced descriptors, the
timestamp value is written into TDES6 and TDES7. The status information is then written to this
transmit descriptor (TDES0). Because the OWN bit is cleared during this step, the CPU now
owns this descriptor. If timestamping was not enabled for this frame, the DMA does not alter
the contents of TDES2/TDES3 or TDES6/TDES7 depending on the descriptor configuration
chosen.
9. The Transmit Interrupt (TI) bit is set in the EMACDMARIS register after transmission completion
of a frame that has Interrupt on Completion set in its last descriptor. The Interrupt on Completion
1595December 13, 2013
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