Datasheet

Figure 24-4. RMII Clock Structure
Ethernet MAC External PHY
MOSC
PTPCEN
RX+
RX-
TX+
TX-
Gated SYSCLK
PTP_REFCLK
MAC Control /
Status Registers
EMACCC
Tiva Cortex-M4
Microcontroller
EN0REF_CLK (50 MHz Clock)
EN0RXDV
EN0TXEN
EN0MDIO
EN0MDC
EN0INTRN
EN0RXD1
EN0RXD0
EN0TXD1
EN0TXD0
Clock
Source
Needed
24.3.2 MII/RMII Interface Signals
The MAC Module has the capability of providing an MII or RMII interface depending on the interface
selected in the Ethernet MAC Peripheral Configuration (EMACPC) register, at offset 0xFC4.
Except for EN0REF_CLK, the signals used for RMII mode are a subset of the MII interface signals.
Thus, Table 24-2 on page 1591 details the MII signals that are used in RMII mode and the RMII function
to which they correspond. In addition, the GPIO pin they are muxed with is listed.
Table 24-2. MII and RMII Interface Signals
GPIORMII Standard Name and FunctionRMIIMII Signal
PM4REF_CLK: Synchronous clock reference for
receive, transmit and control
EN0REF_CLKN/A
PG2N/ANot UsedEN0TXCK
PK7N/ANot UsedEN0TD3
PK6N/ANot UsedEN0TXD2
PG5/PS5TXD1: Transmit Data 1EN0TXD1EN0TXD1
PG4/PS4TXD0: Transmit Data 0EN0TXD0EN0TXD0
PG3/PR7TEX_EN: Transmit EnableEN0TXENEN0TXEN
PN6N/ANot UsedEN0TXER
PA6N/ANot UsedEN0RXCK
PK4N/ANot UsedEN0RXD3
PK5N/ANot UsedEN0RXD2
PQ6/PT1RXD1: Receive Data 1EN0RXD1EN0RXD1
1591December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller