Datasheet

Figure 24-3. MII Clock Structure
Ethernet MAC External PHY
MOSC
PTPCEN
RX+
RX-
TX+
TX-
EN0RXER
EN0RXCK
EN0RXD3
EN0RXDV
EN0TXCK
EN0TXD3
EN0TXER
EN0TXEN
EN0COL
EN0CRS
EN0MDIO
EN0MDC
EN0INTRN
EN0RXD2
EN0RXD1
EN0RXD0
EN0TXD2
EN0TXD1
EN0TXD0
Gated SYSCLK
PTP_REFCLK
MAC Control /
Status Registers
EMACCC
Tiva Cortex-M4
Microcontroller
Typically
25MHz
Crystal
24.3.1.3 RMII Interface
There are three clock sources that interface to the Ethernet MAC in an RMII configuration:
■ Gated system clock (SYSCLK): The SYSCLK signal acts as the clock source to the Control and
Status registers (CSR) of the Ethernet MAC. The SYSCLK frequency for Run, Sleep and Deep
Sleep mode is programmed in the System Control module. Refer to “System Control” on page 230
for more information on programming SYSCLK and enabling the Ethernet MAC.
■ MOSC: A gated version of the MOSC clock is provided as the Precision Time Protocol (PTP)
reference clock (PTPREF_CLK). The MOSC clock source can be a single-ended source on the
OSC0 pin or a crystal on the OSC0 and OSC1 pins. When advanced timestamping is used and
the PTP module has been enabled by setting the PTPCEN bit in the EMACCC register, the MOSC
drives PTPREF_CLK. PTPREF_CLK has a minimum frequency requirement of 5 MHz and a
maximum frequency of 25 MHz. Refer to “IEEE 1588 and Advanced Timestamp
Function” on page 1631 for more information.
■ EN0REF_CLK: When using RMII, a 50 MHz external reference clock must drive the EN0REF_CLK
input signal and the external PHY. Depending on the configuration of the FES bit in the Ethernet
MAC Configuration (EMACCFG) register, the reference clock input (EN0REF_CLK) is divided
by 20 for 10 Mbps or 2 for 100 Mbps operation and used as the clock for receive and transmit
data.
Figure 24-4 on page 1591 depicts the clock inputs to the RMII clock interface.
December 13, 20131590
Texas Instruments-Advance Information
Ethernet Controller