Datasheet

24.3 Functional Description
The Ethernet Controller is made up of the following sub-modules:
■ Clock Control
■ MII/RMII Interface Module
■ DMA Controller
■ Transmit/Receive Controller (TX/RX Controller)
■ Media Access Controller (MAC)
■ AHB Bus Interface
■ PHY Interface
The following sections describe the features and functions of each sub-module.
24.3.1 Ethernet Clock Control
Available clock sources are dependent on the interface chosen. The following sections describe the
clock control for the various interfaces.
24.3.1.1 PHY Interface
The Ethernet Controller Module and Integrated PHY receive two clock inputs:
■ A gated system clock acts as the clock source to the Control and Status registers (CSR) of the
Ethernet MAC. The SYSCLK frequency for Run, Sleep and Deep Sleep mode is programmed
in the System Control module. Refer to “System Control” on page 230 for more information on
programming SYSCLK and enabling the Ethernet MAC.
■ The PHY receives the main oscillator (MOSC) which must be 25 MHz ± 50 ppm for proper
operation. The MOSC source can be a single-ended source or a crystal. Figure 24-2 on page 1589
shows the clock inputs to the Ethernet Controller Module.
December 13, 20131588
Texas Instruments-Advance Information
Ethernet Controller