Datasheet

Register 9: 1-Wire µDMA Control (ONEWIREDMA), offset 0x120
The 1-Wire DMA Control (ONEWIREDMA) register is used to configure the µDMA operation for
1-Wire. This mechanism supports both µDMA write operations, µDMA read operations, small
write/read operations, and scatter-gather support of mixed operations.
Note: This register is cleared when the dma_done signal to the 1-Wire module is asserted by the
µDMA and the DMA bit in the ONEWIRERIS register is set.
1-Wire µDMA Control (ONEWIREDMA)
Base 0x400B.6000
Offset 0x120
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RSTDMAOPSGreserved
RWRWRWRWROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:4
Scatter-Gather Enable
This bit should be enabled when DMAOP = 0x1 and the scatter-gather
method is being used.
This bit self clears after it has performed the µDMA request.
DescriptionValue
No effect0
µDMA is requested at start of operation and all requests after
are on completion of transactions.
1
0RWSG3
µDMA Operation
The programmed operation starts when reset completes if the RST bit
in the ONEWIRECS register is set. If RST is not set, then write requests
the µDMA immediately and read starts on a write to the ONEWIREDATW
register.
DescriptionValue
µDMA disabled0x0
µDMA single read: 1-Wire requests µDMA to read
ONEWIREDATR register after each read transaction.
0x1
µDMA multiple write: 1-Wire requests µDMA to load whenever
the ONEWIREDATW register is empty.
0x2
µDMA multiple read: An initial read occurs and subsequent
reads start after µDMA has read the ONEWIREDATR register.
0x3
0x0RWDMAOP2:1
1531December 13, 2013
Texas Instruments-Advance Information
Tiva
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TM4C129XNCZAD Microcontroller