Datasheet

Register 7: 1-Wire Masked Interrupt Status (ONEWIREMIS), offset 0x108
The 1-Wire Masked Interrupt Status (ONEWIREMIS) register indicates when an unmasked interrupt
has occurred.
1-Wire Masked Interrupt Status (ONEWIREMIS)
Base 0x400B.6000
Offset 0x108
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RSTOPCNOATRSTUCKDMAreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000ROreserved31:5
DMA Done Masked Interrupt Status
DescriptionValue
No interrupt0
A DMA transfer is complete and an unmasked interrupt is
pending.
1
0RODMA4
Stuck Status Masked Interrupt Status
When unmasked, this interrupt indicates a line-hold-low error is detected.
DescriptionValue
No interrupt0
An unmasked Stuck status (line-hold-error) interrupt is detected
and pending.
1
0ROSTUCK3
No Answer-to-Reset Masked Interrupt Status
DescriptionValue
No interrupt0
A No Answer-to-Reset unmasked interrupt is detected from the
last reset and pending.
1
0RONOATR2
Operation Complete Masked Interrupt Status
DescriptionValue
No Interrupt0
An unmasked operation complete interrupt is pending.1
0ROOPC1
December 13, 20131528
Texas Instruments-Advance Information
1-Wire Master Module