Datasheet

RST is not set in the ONEWIREDMA register, the transaction starts. If RST is set, the transaction
starts when reset completes. At the end of the operation, the µDMA is requested to transfer the
data from the ONEWIREDATR register (read).
3. When the µDMA is done, the DMA bit in the ONEWIRERIS register is set, allowing interrupt on
completion by µDMA, and the ONEWIREDMA register is cleared.
It is recommended to enable trigger interrupts for ERR and NOATR when using µDMA so application
is notified if reset or the transaction failed.
The natural model for using scatter-gather is:
1. Enable peripheral-scatter-gather in the µDMA module by programming the DMA Channel
Control Word (DMACHCTL) register.
2. Set the DMAOP to read (not read multiple) and enable scatter gather in the 1-Wire module by
setting the SG bit to 0x1 in the ONEWIREDMA register. This allows use of ONEWDATW register
to push through transactions, with µDMA request being triggered off completion, except for the
first transaction.
3. Scatter gather can then use a combination of write and read as needed.
22.3.9 1-Wire Timing
The 1-Wire module wire control operates using the Precision Internal Oscillator (PIOSC) to provide
a reliable frequency with no need for baud dividers. The register interface operates using the system
clock, which may be a different clock source. However, there is no visible impact from this separate
clock model. Normal rules apply to use of the registers to ensure correct operation. In particular:
■ The control register is used live (not buffered) by the communication engine. Once an operation
is started, it must be allowed to finish before changes are made, such as starting a new operation
or changing speed. The status bits in the ONEWIRECS register notify the application if the
transaction is busy or if a line-hold-low error is detected. When the last write, read or read/write
has occurred, the OPC bit is set in the ONEWIRERIS register.
■ Data read by the 1-Wire Master is not valid or meaningful until the 1-Wire module signals that
the data is ready (via interrupt, DMA, and status).
■ Data written should be written before the operation is started and then should not be re-written
until the 1-Wire module signals the data has been written (via interrupt, DMA, and status).
■ The 1-Wire Timing Override (ONEWIRETIM) register should not be changed while a transaction
is taking place.
The ONEWIREIM, ONEWIRERIS and ONEWIREMIS registers may be written and read at any time
with no risk.
22.4 Initialization and Configuration
The whole block may be enabled or disabled using the system control registers. The following
example shows how to enable, force a reset and send a command.
1. Enable the 1-Wire Module by writing a value of 0x0000.0001 to the 1-Wire Run Mode Clock
Gating Control (RCGCOWIRE) register in the System Control Module, see page 419.
December 13, 20131514
Texas Instruments-Advance Information
1-Wire Master Module