Datasheet

Table 22-3. Bit Field Definitions for 1-Wire Timing and Override (ONEWIRETIM) Register
(continued)
Default
(overdrive)
Default
(normal)
ScaleRange (if used)MeaningName
2.5 µs10 µs1 µs units1 to 15 µsAmount of time to hold line high after a write 0
(rest)
a
W0REST
1 µs10 µs1 µs units1 to 15 µsAmount of time after 1-Wire has released the
line to sample slave holding line
W1SAM
70 µs480 µs32 µs units32 to 2016 µsAmount of time to drive and hold line low for a
reset. Allow for an additional 2-µs pre-reset
period
RSTTIM
48 µs240 µs16 µs units16 to 496 µsPeriod of answer-to-reset or rest. The ATRSAM
bit value must be considered when programming
this field. ATRTIM must be greater than ATRSAM
to avoid a STUCK fault generation
ATRTIM
2 µs10 µs
b
8 µs units8 to 120 µsPeriod in which first sample occurs in
answer-to-reset (after line goes high). If the
SKATR bit is set in the ONEWIRECS register,
this value indicates the rest period after reset
ATRSAM
a. If W0TIM has been programmed to a non-default value, W0REST must be programmed for correct functionality.
b. ATRSAM is the first sample. If the line is high, it continues sampling for the rest of ATRTIM period to see if goes low. This
subsequent sampling is every 62.5 ns. Thus, this value must be long enough to be sure the line has floated high, but
does not have to be after the time the slaves have driven low. This rule is different than a single sample model, which
can be too late or miss on long lines.
22.3.5 Command Protocol
The standard 1-Wire protocol has commands to be used after a reset. These commands normally
include slave selection and detection. However, many 1-Wire buses only have one slave, and in
that case, those mechanisms can be skipped. If slave management is needed, a small software
stack can be used to handle these operations. Other protocols can also be easily supported, whether
byte-oriented (as normal) or bit-oriented. To support an alternative protocol, it is usually necessary
to override some or all of the timing and may be necessary to disable the answer-to-reset mechanism
using the SKATR bit in the ONEWIRECS register. The module is designed to support the most
common uses of 1-Wire, including a mechanism to allow a reset followed by an operation of 1, 2,
3, or 4 bytes through the SZ bit in the ONEWIRECS register. Additionally, the OP bit supports a
write/read model to allow a mix of write and read in one transaction. Although nominally mixed mode
allows for a mix of write and read bytes, it can be used down to the bit level.
The following represents some typical operation flows:
1. To only send a reset, the RST bit of the ONEWIRECS register is set, performing a reset and
triggering an interrupt if enabled. If there is no answer-to-reset, the NOATR status bit is set and
the corresponding interrupt bit can be set as well.
2. The SZ and OP fields of the ONEWIRECS register are used to perform a write, a read, or a
combination. For small transactions, the SZ encoding can be programmed for processing of up
to 4 bytes in one transaction. For larger transactions, the OP field can be used multiple times.
The OPC raw interrupt bit is used to notify when a transaction is complete.
3. To perform a reset and then a transaction, both the RST and OP/SZ fields of the ONEWIRECS
register are configured. The reset runs to completion and then the transaction starts. The interrupt
is used to notify when both are done.
1511December 13, 2013
Texas Instruments-Advance Information
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TM4C129XNCZAD Microcontroller