Datasheet

Figure 10-4. GPIODATA Read Example ................................................................................. 780
Figure 11-1. EPI Block Diagram ............................................................................................. 848
Figure 11-2. SDRAM Non-Blocking Read Cycle ...................................................................... 856
Figure 11-3. SDRAM Normal Read Cycle ............................................................................... 856
Figure 11-4. SDRAM Write Cycle ........................................................................................... 857
Figure 11-5. iRDY Access Stalls, IRDYDLY==01, 10, 11 .......................................................... 868
Figure 11-6. iRDY Signal Connection ..................................................................................... 868
Figure 11-7. PSRAM Burst Read ........................................................................................... 870
Figure 11-8. PSRAM Burst Write ........................................................................................... 871
Figure 11-9. Read Delay During Refresh Event ...................................................................... 872
Figure 11-10. Write Delay During Refresh Event ....................................................................... 872
Figure 11-11. Example Schematic for Muxed Host-Bus 16 Mode ............................................... 873
Figure 11-12. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 876
Figure 11-13. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 876
Figure 11-14. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH
= 0, RDHIGH = 0 ............................................................................................... 877
Figure 11-15. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual or
Quad CSn ......................................................................................................... 877
Figure 11-16. Continuous Read Mode Accesses ...................................................................... 877
Figure 11-17. Write Followed by Read to External FIFO ............................................................ 878
Figure 11-18. Two-Entry FIFO ................................................................................................. 878
Figure 11-19. Single-Cycle Single Write Access, FRM50=0, FRMCNT=0, WR2CYC=0 ............... 881
Figure 11-20. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, WR2CYC=1 ............... 882
Figure 11-21. Read Accesses, FRM50=0, FRMCNT=0 ............................................................. 882
Figure 11-22. FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 883
Figure 11-23. FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 883
Figure 11-24. FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 883
Figure 11-25. FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 883
Figure 11-26. FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 884
Figure 11-27. FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 884
Figure 11-28. EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 884
Figure 11-29. EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 885
Figure 13-1. AES Block Diagram ........................................................................................... 987
Figure 13-2. AES - ECB Feedback Mode ............................................................................... 991
Figure 13-3. AES - CBC Feedback Mode ............................................................................... 992
Figure 13-4. AES Encryption With CTR/ICM Mode .................................................................. 992
Figure 13-5. AES - CFB Feedback Mode ............................................................................... 993
Figure 13-6. AES - F8 Mode .................................................................................................. 994
Figure 13-7. AES - XTS Operation ......................................................................................... 994
Figure 13-8. AES - F9 Operation ........................................................................................... 995
Figure 13-9. AES - CBC-MAC Authentication Mode ................................................................ 996
Figure 13-10. AES - GCM Operation ........................................................................................ 997
Figure 13-11. AES - CCM Operation ........................................................................................ 998
Figure 13-12. AES Polling Mode ............................................................................................ 1005
Figure 13-13. AES Interrupt Service ....................................................................................... 1007
Figure 14-1. DES Block Diagram ......................................................................................... 1039
Figure 14-2. DES - ECB Feedback Mode ............................................................................. 1042
Figure 14-3. DES3DES - CBC Feedback Mode .................................................................... 1042
15December 13, 2013
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TM4C129XNCZAD Microcontroller