Datasheet

DescriptionResetTypeNameBit/Field
Receive FIFO Request Interrupt Mask
DescriptionValue
No interrupt.0
An unmasked Receive FIFO Request interrupt was signaled
and is pending.
1
This bit is cleared by writing a 1 to the RXIC bit in the I2CMICR register.
0RORXMIS9
Transmit Request Interrupt Mask
DescriptionValue
No interrupt.0
An unmasked Transmit FIFO Request interrupt was signaled
and is pending.
1
This bit is cleared by writing a 1 to the TXIC bit in the I2CMICR register.
0ROTXMIS8
Arbitration Lost Interrupt Mask
DescriptionValue
No interrupt.0
An unmasked Arbitration Lost interrupt was signaled and is
pending.
1
This bit is cleared by writing a 1 to the ARBLOSTIC bit in the I2CMICR
register.
0ROARBLOSTMIS7
STOP Detection Interrupt Mask
DescriptionValue
No interrupt.0
An unmasked STOP Detection interrupt was signaled and is
pending.
1
This bit is cleared by writing a 1 to the STOPIC bit in the I2CMICR
register.
0ROSTOPMIS6
START Detection Interrupt Mask
DescriptionValue
No interrupt.0
An unmasked START Detection interrupt was signaled and is
pending.
1
This bit is cleared by writing a 1 to the STARTIC bit in the I2CMICR
register.
0ROSTARTMIS5
1471December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller