Datasheet

21.3.6.2 I
2
C Slave Command Sequences
Figure 21-15 on page 1446 presents the command sequence available for the I
2
C slave.
Figure 21-15. Slave Command Sequence
Idle
Write OWN Slave
Address to
I2CSOAR
Write -------1
to I2CSCSR
Read I2CSCSR
RREQ bit=1?
Read data from
I2CSDR
YES
TREQ bit=1?
NO
Write data to
I2CSDR
YES
NO
FBR is
also valid
21.4 Initialization and Configuration
21.4.1 Configure the I
2
C Module to Transmit a Single Byte as a Master
The following example shows how to configure the I
2
C module to transmit a single byte as a master.
This assumes the system clock is 20 MHz.
1. Enable the I
2
C clock using the RCGCI2C register in the System Control module (see page 407).
2. Enable the clock to the appropriate GPIO module via the RCGCGPIO register in the System
Control module (see page 398). To find out which GPIO port to enable, refer to Table
31-5 on page 2087.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register (see page 801). To determine which GPIOs to configure, see Table
31-4 on page 2070.
December 13, 20131446
Texas Instruments-Advance Information
Inter-Integrated Circuit (I
2
C) Interface