Datasheet

3 Cortex-M4 Peripherals
This chapter provides information on the Tiva™ C Series implementation of the Cortex-M4 processor
peripherals, including:
■ SysTick (see page 145)
Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible
control mechanism.
■ Nested Vectored Interrupt Controller (NVIC) (see page 146)
– Facilitates low-latency exception and interrupt handling
– Controls power management
– Implements system control registers
■ System Control Block (SCB) (see page 147)
Provides system implementation information and system control, including configuration, control,
and reporting of system exceptions.
■ Memory Protection Unit (MPU) (see page 147)
Supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU
provides full support for protection regions, overlapping protection regions, access permissions,
and exporting memory attributes to the system.
■ Floating-Point Unit (FPU) (see page 152)
Fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and
square root operations. It also provides conversions between fixed-point and floating-point data
formats, and floating-point constant instructions.
Table 3-1 on page 144 shows the address map of the Private Peripheral Bus (PPB). Some peripheral
register regions are split into two address regions, as indicated by two addresses listed.
Table 3-1. Core Peripheral Register Regions
Description (see page ...)Core PeripheralAddress
145System Timer0xE000.E010-0xE000.E01F
146Nested Vectored Interrupt Controller0xE000.E100-0xE000.E4EF
0xE000.EF00-0xE000.EF03
147System Control Block0xE000.E008-0xE000.E00F
0xE000.ED00-0xE000.ED3F
147Memory Protection Unit0xE000.ED90-0xE000.EDB8
152Floating Point Unit0xE000.EF30-0xE000.EF44
3.1 Functional Description
This chapter provides information on the Tiva™ C Series implementation of the Cortex-M4 processor
peripherals: SysTick, NVIC, SCB, MPU, FPU.
December 13, 2013144
Texas Instruments-Advance Information
Cortex-M4 Peripherals