Datasheet

■ Transmit FIFO is empty (TXFERIS bit)
■ Receive FIFO is full (RXFFRIS bit)
Interrupts are generated when the following conditions are observed in the Slave Module:
■ Slave transaction received (DATARIS bit)
■ Slave transaction requested (DATARIS bit)
■ Slave next byte transfer request (DATARIS bit)
■ Stop condition on bus detected (STOPRIS bit)
■ Start condition on bus detected (STARTRIS bit)
■ RX DMA interrupt pending (DMARXRIS bit)
■ TX DMA interrupt pending (DMATXRIS bit)
■ Programmable trigger value for FIFO has been reached and a TX FIFO request interrupt is
pending (TXRIS bit)
■ Programmable trigger value for FIFO has been reached and a RX FIFO request interrupt is
pending (RXRIS bit)
■ Transmit FIFO is empty (TXFERIS bit)
■ Receive FIFO is full (RXFFRIS bit)
The I
2
C master and I
2
C slave modules have separate interrupt registers. Interrupts can be masked
by clearing the appropriate bit in the I2CMIMR or I2CSIMR register. Note that the RIS bit in the
Master Raw Interrupt Status (I2CMRIS) register and the DATARIS bit in the Slave Raw Interrupt
Status (I2CSRIS) register have multiple interrupt causes including a next byte transfer request
interrupt. This interrupt is generated when both master and slave are requesting a receive or transmit
transaction.
21.3.4 Loopback Operation
The I
2
C modules can be placed into an internal loopback mode for diagnostic or debug work by
setting the LPBK bit in the I
2
C Master Configuration (I2CMCR) register. In loopback mode, the
SDA and SCL signals from the master and are tied to the SDA and SCL signals of the slave module
to allow internal testing of the device without having to go through I/O.
21.3.5 FIFO and µDMA Operation
Both the master and the slave module have the capability to access two 8-byte FIFOs that can be
used in conjunction with the µDMA for fast transfer of data. The transmit (TX) FIFO and receive
(RX) FIFO can be independently assigned to either the I
2
C master or I
2
C slave. Thus, the following
FIFO assignments are allowed:
■ The transmit and receive FIFOs can be assigned to the master
■ The transmit and receive FIFOs can be assigned to the slave
December 13, 20131436
Texas Instruments-Advance Information
Inter-Integrated Circuit (I
2
C) Interface