Datasheet

Table 21-2. Examples of I
2
C Master Timer Period Versus Speed Mode (continued)
Fast Mode
Plus
Timer
Period
Fast ModeTimer PeriodStandard ModeTimer PeriodSystem Clock
--312 Kbps0x0189 Kbps0x0612.5 MHz
--278 Kbps0x0293 Kbps0x0816.7 MHz
--333 Kbps0x02100 Kbps0x0920 MHz
--312 Kbps0x0396.2 Kbps0x0C25 MHz
--330 Kbps0x0497.1 Kbps0x1033 MHz
1000 Kbps0x01400 Kbps0x04100 Kbps0x1340 MHz
833 Kbps0x02357 Kbps0x06100 Kbps0x1850 MHz
1000 Kbps0x03400 Kbps0x09100 Kbps0x2780 MHz
1000 Kbps0x04385 Kbps0x0C100 Kbps0x31100 MHz
PendingPendingPendingPendingPendingPending120 MHz
21.3.2.2 High-Speed Mode
The TM4C129XNCZAD I
2
C peripheral has support for High-speed operation as both a master and
slave. High-Speed mode is configured by setting the HS bit in the I
2
C Master Control/Status
(I2CMCS) register. High-Speed mode transmits data at a high bit rate with a 66.6%/33.3% duty
cycle, but communication and arbitration are done at Standard, Fast mode, or Fast-mode plus
speed, depending on which is selected by the user. When the HS bit in the I2CMCS register is set,
current mode pull-ups are enabled.
The clock period can be selected using the equation below, but in this case, SCL_LP=2 and
SCL_HP=1.
SCL_PERIOD = 2 × (1 + TIMER_PRD) × (SCL_LP + SCL_HP) × CLK_PRD
So for example:
CLK_PRD = 25 ns
TIMER_PRD = 1
SCL_LP=2
SCL_HP=1
yields a SCL frequency of:
1/T = 3.33 Mhz
Table 21-3 on page 1434 gives examples of timer period and system clock in High-Speed mode. Note
that the HS bit in the I2CMTPR register needs to be set for the TPR value to be used in High-Speed
mode.
Table 21-3. Examples of I
2
C Master Timer Period in High-Speed Mode
Transmission ModeTimer PeriodSystem Clock
3.33 Mbps0x0140 MHz
2.77 Mbps0x0250 MHz
3.33 Mbps0x0380 MHz
When operating as a master, the protocol is shown in Figure 21-7. The master is responsible for
sending a master code byte in either Standard (100 Kbps) or Fast-mode (400 Kbps) before it begins
December 13, 20131434
Texas Instruments-Advance Information
Inter-Integrated Circuit (I
2
C) Interface