Datasheet

set. When the master sends a Quick Command with the R/S (data) bit set, the DATARIS bit is set
to notify the slave to write a data byte to I2CSDR in which bit 7 is set. A “dummy write” of 0xFF to
the I2CSDR register is recommended. After the write to I2CSDR, the STOP interrupt is asserted
and the QCMDST and QCMDRW bits are set in the I2CSCSR register to indicate that a quick command
read occurred and the last transaction was a Quick Command. Therefore, when the slave must
receive a Quick Command, it should be expecting such a command because it must write the
I2CSDR with a specific value when R/S is set.
21.3.2 Available Speed Modes
The I
2
C bus can run in Standard mode (100 kbps), Fast mode (400 kbps), Fast mode plus (1 Mbps)
or High-Speed mode (3.4 Mbps, provided correct system clock frequency is set and there is
appropriate pull strength on SCL and SDA lines). The selected mode should match the speed of
the other I
2
C devices on the bus.
21.3.2.1 Standard, Fast, and Fast Plus Modes
Standard, Fast, and Fast Plus modes are selected using a value in the I
2
C Master Timer Period
(I2CMTPR) register that results in an SCL frequency of 100 kbps for Standard mode, 400 kbps for
Fast mode, or 1 Mbps for Fast mode plus.
The I
2
C clock rate is determined by the parameters CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP
where:
CLK_PRD is the system clock period
SCL_LP is the low phase of SCL (fixed at 6)
SCL_HP is the high phase of SCL (fixed at 4)
TIMER_PRD is the programmed value in the I2CMTPR register (see page 1462). This value is
determined by replacing the known variables in the equation below and solving for TIMER_PRD.
The I
2
C clock period is calculated as follows:
SCL_PERIOD = 2 × (1 + TIMER_PRD) × (SCL_LP + SCL_HP) × CLK_PRD
For example:
CLK_PRD = 50 ns
TIMER_PRD = 2
SCL_LP=6
SCL_HP=4
yields a SCL frequency of:
1/SCL_PERIOD = 333 Khz
Table 21-2 gives examples of the timer periods that should be used to generate Standard, Fast
mode, and Fast mode plus SCL frequencies based on various system clock frequencies.
Table 21-2. Examples of I
2
C Master Timer Period Versus Speed Mode
Fast Mode
Plus
Timer
Period
Fast ModeTimer PeriodStandard ModeTimer PeriodSystem Clock
----100 Kbps0x014 MHz
----100 Kbps0x026 MHz
1433December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller