Datasheet

21.2 Signal Description
The following table lists the external signals of the I
2
C interface and describes the function of each.
The I
2
C interface signals are alternate functions for some GPIO signals and default to be GPIO
signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible
GPIO pin placements for the I
2
C signals. The AFSEL bit in the GPIO Alternate Function Select
(GPIOAFSEL) register (page 801) should be set to choose the I
2
C function. The number in
parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control
(GPIOPCTL) register (page 818) to assign the I
2
C signal to the specified GPIO port pin. Note that
the I2CSDA pin should be set to open drain using the GPIO Open Drain Select (GPIOODR) register.
For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 771.
Table 21-1. I2C Signals (212BGA)
DescriptionBuffer TypePin TypePin Mux / Pin
Assignment
Pin NumberPin Name
I
2
C module 0 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
ODI/OPB2 (2)A17I2C0SCL
I
2
C module 0 data.ODI/OPB3 (2)B17I2C0SDA
I
2
C module 1 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
ODI/OPG0 (2)
PR0 (2)
N15
N5
I2C1SCL
I
2
C module 1 data.ODI/OPG1 (2)
PR1 (2)
T14
N4
I2C1SDA
I
2
C module 2 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
ODI/OPG2 (2)
PL1 (2)
PN5 (3)
PP5 (2)
PR2 (2)
V11
H19
B9
B12
N2
I2C2SCL
I
2
C module 2 data.ODI/OPG3 (2)
PL0 (2)
PN4 (3)
PP6 (2)
PR3 (2)
M16
G16
A10
B8
V8
I2C2SDA
I
2
C module 3 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
ODI/OPG4 (2)
PK4 (2)
PR4 (2)
K17
U19
P3
I2C3SCL
I
2
C module 3 data.ODI/OPG5 (2)
PK5 (2)
PR5 (2)
K15
V17
P2
I2C3SDA
I
2
C module 4 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
ODI/OPG6 (2)
PK6 (2)
PR6 (2)
V12
V16
W9
I2C4SCL
I
2
C module 4 data.ODI/OPG7 (2)
PK7 (2)
PR7 (2)
U14
W16
R10
I2C4SDA
I
2
C module 5 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
ODI/OPB0 (2)
PB4 (2)
A16
C6
I2C5SCL
I
2
C module 5 data.ODI/OPB1 (2)
PB5 (2)
B16
B6
I2C5SDA
December 13, 20131426
Texas Instruments-Advance Information
Inter-Integrated Circuit (I
2
C) Interface