Datasheet

21 Inter-Integrated Circuit (I
2
C) Interface
The Inter-Integrated Circuit (I
2
C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL), and interfaces to external I
2
C devices such as
serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I
2
C
bus may also be used for system testing and diagnostic purposes in product development and
manufacturing. The TM4C129XNCZAD microcontroller includes providing the ability to communicate
(both transmit and receive) with other I
2
C devices on the bus.
The TM4C129XNCZAD controller includes I
2
C modules with the following features:
■ Devices on the I
2
C bus can be designated as either a master or a slave
– Supports both transmitting and receiving data as either a master or a slave
– Supports simultaneous master and slave operation
■ Four I
2
C modes
– Master transmit
– Master receive
– Slave transmit
– Slave receive
■ Two 8-entry FIFOs for receive and transmit data
– FIFOs can be independently assigned to master or slave
■ Four transmission speeds:
– Standard (100 Kbps)
– Fast-mode (400 Kbps)
– Fast-mode plus (1 Mbps)
– High-speed mode (3.33 Mbps)
■ Glitch suppression
■ SMBus support through software
– Clock low timeout interrupt
– Dual slave address capability
– Quick command capability
■ Master and slave interrupt generation
– Master generates interrupts when a transmit or receive operation completes (or aborts due
to an error)
December 13, 20131424
Texas Instruments-Advance Information
Inter-Integrated Circuit (I
2
C) Interface