Datasheet

Register 12: QSSI Clock Configuration (SSICC), offset 0xFC8
The SSICC register controls the baud clock source for the QSSI module.
Note: If ALTCLK is used for the QSSI baud clock, the system clock frequency must be at least
twice that of the ALTCLK programmed value in Run mode.
QSSI Clock Configuration (SSICC)
QSSI0 base: 0x4000.8000
QSSI1 base: 0x4000.9000
QSSI2 base: 0x4000.A000
QSSI3 base: 0x4000.B000
Offset 0xFC8
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CSreserved
RWRWRWRWROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:4
QSSI Baud Clock Source
The following table specifies the source that generates for the QSSI
baud clock:
DescriptionValue
System clock (based on clock source and divisor factor
programmed in RSCLKCFG register in the System Control
Module)
0x0
reserved0x1-0x4
Alternate clock source as defined by ALTCLKCFG register
in System Control Module.
0x5
Reserved0x6 - 0xF
0RWCS3:0
1411December 13, 2013
Texas Instruments-Advance Information
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TM4C129XNCZAD Microcontroller