Datasheet

DescriptionResetTypeNameBit/Field
QSSI Transmit FIFO Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
An unmasked interrupt was signaled due to the transmit FIFO
being half empty or less (if the EOT bit is clear) or due to the
transmission of the last data bit (if the EOT bit is set).
1
This bit is cleared when the transmit FIFO is more than half empty (if
the EOT bit is clear) or when it has any data in it (if the EOT bit is set).
0ROTXMIS3
QSSI Receive FIFO Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
An unmasked interrupt was signaled due to the receive FIFO
being half full or more.
1
This bit is cleared when the receive FIFO is less than half full.
0RORXMIS2
QSSI Receive Time-Out Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
An unmasked interrupt was signaled due to the receive time
out.
1
This bit is cleared when a 1 is written to the RTIC bit in the SSI Interrupt
Clear (SSIICR) register.
0RORTMIS1
QSSI Receive Overrun Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
An unmasked interrupt was signaled due to the receive FIFO
overflowing.
1
This bit is cleared when a 1 is written to the RORIC bit in the SSI
Interrupt Clear (SSIICR) register.
0RORORMIS0
1407December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller