Datasheet

DescriptionResetTypeNameBit/Field
QSSI Transmit FIFO Raw Interrupt Status
DescriptionValue
No interrupt.0
If the EOT bit in the SSICR1 register is clear, the transmit FIFO
is half empty or less.
If the EOT bit is set, the transmit FIFO is empty, and the last bit
has been transmitted out of the serializer.
1
This bit is cleared when the transmit FIFO is more than half full (if the
EOT bit is clear) or when it has any data in it (if the EOT bit is set).
1ROTXRIS3
QSSI Receive FIFO Raw Interrupt Status
DescriptionValue
No interrupt.0
The receive FIFO is half full or more.1
This bit is cleared when the receive FIFO is less than half full.
0RORXRIS2
QSSI Receive Time-Out Raw Interrupt Status
DescriptionValue
No interrupt.0
The receive time-out has occurred.1
This bit is cleared when a 1 is written to the RTIC bit in the SSI Interrupt
Clear (SSIICR) register.
0RORTRIS1
QSSI Receive Overrun Raw Interrupt Status
DescriptionValue
No interrupt.0
The receive FIFO has overflowed1
This bit is cleared when a 1 is written to the RORIC bit in the SSI
Interrupt Clear (SSIICR) register.
0RORORRIS0
1405December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller