Datasheet

Register 7: QSSI Raw Interrupt Status (SSIRIS), offset 0x018
The SSIRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt prior to masking. A write has no effect.
QSSI Raw Interrupt Status (SSIRIS)
QSSI0 base: 0x4000.8000
QSSI1 base: 0x4000.9000
QSSI2 base: 0x4000.A000
QSSI3 base: 0x4000.B000
Offset 0x018
Type RO, reset 0x0000.0008
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RORRISRTRISRXRISTXRIS
DMARXRISDMATXRIS
EOTRISreserved
ROROROROROROROROROROROROROROROROType
0001000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:7
End of Transmit Raw Interrupt Status
DescriptionValue
No interrupt.0
The transmit FIFO is empty, and the last bit has been transmitted
out of the serializer.
1
This bit is cleared when a 1 is written to the EOTIC bit in the SSI
Interrupt Clear (SSIICR) register.
0ROEOTRIS6
QSSI Transmit DMA Raw Interrupt Status
DescriptionValue
No interrupt.0
The transmit DMA has completed.1
This bit is cleared when a 1 is written to the DMATXIC bit in the SSI
Interrupt Clear (SSIICR) register.
0RODMATXRIS5
QSSI Receive DMA Raw Interrupt Status
DescriptionValue
No interrupt.0
The receive DMA has completed.1
This bit is cleared when a 1 is written to the DMARXIC bit in the SSI
Interrupt Clear (SSIICR) register.
0RODMARXRIS4
December 13, 20131404
Texas Instruments-Advance Information
Quad Synchronous Serial Interface (QSSI)