Datasheet

Register 6: QSSI Interrupt Mask (SSIIM), offset 0x014
The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits
are cleared on reset.
On a read, this register gives the current value of the mask on the corresponding interrupt. Setting
a bit clears the mask, enabling the interrupt to be sent to the interrupt controller. Clearing a bit sets
the corresponding mask, preventing the interrupt from being signaled to the controller.
QSSI Interrupt Mask (SSIIM)
QSSI0 base: 0x4000.8000
QSSI1 base: 0x4000.9000
QSSI2 base: 0x4000.A000
QSSI3 base: 0x4000.B000
Offset 0x014
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RORIMRTIMRXIMTXIMDMARXIMDMATXIMEOTIMreserved
RWRWRWRWRWRWRWROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:7
End of Transmit Interrupt Mask
DescriptionValue
The end of transmit interrupt is masked.0
The end of transmit interrupt is not masked.1
0RWEOTIM6
QSSI Transmit DMA Interrupt Mask
DescriptionValue
The transmit DMA interrupt is masked.0
The transmit DMA interrupt is not masked.1
0RWDMATXIM5
QSSI Receive DMA Interrupt Mask
DescriptionValue
The receive DMA interrupt is masked.0
The receive DMA interrupt is not masked.1
0RWDMARXIM4
QSSI Transmit FIFO Interrupt Mask
DescriptionValue
The transmit FIFO interrupt is masked.0
The transmit FIFO interrupt is not masked.1
0RWTXIM3
December 13, 20131402
Texas Instruments-Advance Information
Quad Synchronous Serial Interface (QSSI)