Datasheet

List of Figures
Figure 1-1. Tiva
™
TM4C129XNCZAD Microcontroller High-Level Block Diagram ...................... 60
Figure 2-1. CPU Block Diagram ............................................................................................. 91
Figure 2-2. TPIU Block Diagram ............................................................................................ 92
Figure 2-3. Cortex-M4F Register Set ...................................................................................... 95
Figure 2-4. Bit-Band Mapping .............................................................................................. 120
Figure 2-5. Data Storage ..................................................................................................... 121
Figure 2-6. Vector Table ...................................................................................................... 129
Figure 2-7. Exception Stack Frame ...................................................................................... 132
Figure 3-1. SRD Use Example ............................................................................................. 150
Figure 3-2. FPU Register Bank ............................................................................................ 153
Figure 4-1. JTAG Module Block Diagram .............................................................................. 218
Figure 4-2. Test Access Port State Machine ......................................................................... 222
Figure 4-3. IDCODE Register Format ................................................................................... 228
Figure 4-4. BYPASS Register Format ................................................................................... 228
Figure 4-5. Boundary Scan Register Format ......................................................................... 228
Figure 5-1. Basic RST Configuration .................................................................................... 234
Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 234
Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 234
Figure 5-4. Power Architecture ............................................................................................ 240
Figure 5-5. Main Clock Tree ................................................................................................ 243
Figure 5-6. Module Clock Selection ...................................................................................... 252
Figure 7-1. Hibernation Module Block Diagram ..................................................................... 563
Figure 7-2. Using a Crystal as the Hibernation Clock Source with a Single Battery Source ...... 567
Figure 7-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON
Mode ................................................................................................................ 567
Figure 7-4. Using a Regulator for Both V
DD
and V
BAT
............................................................ 568
Figure 7-5. Counter Behavior with a TRIM Value of 0x8002 ................................................... 572
Figure 7-6. Counter Behavior with a TRIM Value of 0x7FFC .................................................. 572
Figure 7-7. Tamper Block Diagram ....................................................................................... 572
Figure 7-8. Tamper Pad with Glitch Filtering ......................................................................... 573
Figure 8-1. Internal Memory Block Diagram .......................................................................... 631
Figure 8-2. Flash Memory Configuration ............................................................................... 635
Figure 8-3. Single 256-Bit Prefetch Buffer Set ....................................................................... 636
Figure 8-4. Four 256-Bit Prefetch Buffer Configuration .......................................................... 636
Figure 8-5. Single Cycle Access, 0 Wait States ..................................................................... 637
Figure 8-6. Prefetch Fills from Flash ..................................................................................... 638
Figure 8-7. Mirror Mode Function ......................................................................................... 639
Figure 9-1. μDMA Block Diagram ......................................................................................... 708
Figure 9-2. Example of Ping-Pong μDMA Transaction ........................................................... 715
Figure 9-3. Memory Scatter-Gather, Setup and Configuration ................................................ 717
Figure 9-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................. 718
Figure 9-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 720
Figure 9-6. Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 721
Figure 10-1. Digital I/O Pads ................................................................................................. 778
Figure 10-2. Analog/Digital I/O Pads ...................................................................................... 779
Figure 10-3. GPIODATA Write Example ................................................................................. 780
December 13, 201314
Texas Instruments-Advance Information
Table of Contents