Datasheet

DescriptionResetTypeNameBit/Field
QSSI Direction of Operation
DescriptionValue
TX (Transmit Mode) write direction0
RX (Receive Mode) read direction1
0RWDIR8
QSSI Mode
DescriptionValue
Legacy SSI mode0x0
Bi-SSI mode0x1
Quad-SSI Mode0x2
Advanced SSI Mode with 8-bit packet size0x3
0x0RWMODE7:6
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved5
End of Transmission
This bit is only valid for Master mode devices and operations (MS = 0x0).
DescriptionValue
The TXRIS interrupt indicates that the transmit FIFO is half full
or less.
0
The End of Transmit interrupt mode for the TXRIS interrupt is
enabled.
1
Note: In Freescale SPI mode only, a condition can be created where
an EOT interrupt is generated for every byte transferred even
if the FIFO is full. If the EOT bit has been set to 0 in an
integrated slave QSSI and the µDMA has been configured to
transfer data from this QSSI to a Master QSSI on the device
using external loopback, an EOT interrupt is generated by
the QSSI slave for every byte even if the FIFO is full.
0RWEOT4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3
QSSI Master/Slave Select
This bit selects Master or Slave mode and can be modified only when
the QSSI is disabled (SSE=0).
DescriptionValue
The QSSI is configured as a master.0
The QSSI is configured as a slave.1
0RWMS2
December 13, 20131396
Texas Instruments-Advance Information
Quad Synchronous Serial Interface (QSSI)