Datasheet

The configuration sequence would be as follows:
1. Ensure that the SSE bit in the SSICR1 register is clear.
2. Write the SSICR1 register with a value of 0x0000.0000.
3. Write the SSICPSR register with a value of 0x0000.0002.
4. Write the SSICR0 register with a value of 0x0000.09C7.
5. The QSSI is then enabled by setting the SSE bit in the SSICR1 register.
20.4.1 Enhanced Mode Configuration
If the QSSI module supports the Advanced/Bi-/Quad features, then these modes can be enabled
after initializing the QSSI module. Below is an example of configuring the QSSI to transmit two data
bytes in Advanced SSI mode followed by 2 bytes in Bi-SSI mode:
1. Set the MODE bit to 0x3, and the FSSHLDFM bit to 1 in the SSICR1 register. To operate in the
master mode, program the MS bit to 0. Program the remaining bits in the SSICR0 and SSICR1
register to relevant values.
2. Write one data byte to the TX FIFO; set the EOM bit to 1 and write the second data byte to the
Tx FIFO.
3. Set the MODE bit to 0x1 and the FSSHLDFM bit to 1 in the SSICR1 register. To operate in the
master mode, program the MS bit to 0. Program the remaining bits in the SSICR0 and SSICR1
register to relevant values.
4. Fill the Tx FIFO with one data byte.
5. Set the EOM bit in the SSICR1 register.
6. Fill the Tx FIFO with one data byte.
20.5 Register Map
Table 20-5 on page 1391 lists the QSSI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that QSSI module’s base address:
■ QSSI0: 0x4000.8000
■ QSSI1: 0x4000.9000
■ QSSI2: 0x4000.A000
■ QSSI3: 0x4000.B000
Note that the QSSI module clock must be enabled before the registers can be programmed (see
page 406). The Rn bit of the PRSSI register must be read as 0x1 before any QSSI module registers
are accessed.
Table 20-5. SSI Register Map
See
page
DescriptionResetTypeNameOffset
1393QSSI Control 00x0000.0000RWSSICR00x000
1391December 13, 2013
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TM4C129XNCZAD Microcontroller