Datasheet

In the case of a single word transfer, after all bits have been transferred, the SSInFss line is returned
to its idle High state one SSInClk period after the last bit has been captured.
For continuous back-to-back transfers, the SSInFss pin is held Low between successive data
words, and termination is the same as that of the single word transfer.
20.3.7.5 Freescale SPI Frame Format with SPO=1 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and
SPH=0 are shown in Figure 20-7 on page 1387 and Figure 20-8 on page 1387.
Note: This Freescale SPI frame format configuration is only available when operating in Legacy
SSI mode of operation.
Figure 20-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
SSInClk
SSInFss
SSInRx
SSInTx
QMSB
MSB
LSB
LSB
4 to 16 bits
Note: Q is undefined.
Figure 20-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0
SSInClk
SSInFss
SSInTx/SSInRx
MSB LSB
LSB
MSB
4 to 16 bits
In this configuration, during idle periods:
■ SSInClk is forced High
■ SSInFss is forced High
■ The transmit data line SSInDAT0/SSInTX is arbitrarily forced Low
■ When the QSSI is configured as a master, it enables the SSInClk pad
■ When the QSSI is configured as a slave, it disables the SSInClk pad
1387December 13, 2013
Texas Instruments-Advance Information
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TM4C129XNCZAD Microcontroller