Datasheet

Table 20-3. SSInFss Functionality
DescriptionFSSHLDFRMMode
For Freescale format, with SPH = 0, the SSInFss signal is asserted low between
continuous transfers. For SPH = 1, the SSInFss signal is deasserted (high) between
continuous transfers.
For TI format, the SSInFss signal is deasserted (high) after every data transfer.
0
Legacy Mode
For Freescale format with any SPH value, the SSInFss signal is forced high between
continuous transfers; it is asserted low when there is available data in the Tx FIFO;
otherwise it is forced high to be ready for a new frame
1
SSInFss is asserted low after every byte of data0
Advanced/Bi-/Quad-
SSI Mode
New data written to the TX FIFO notifies SSInFss to assert low until the Tx FIFO is
empty.
1
20.3.5 High Speed Clock Operation
In master mode, QSSI module can enable a high speed clock by setting the HSCLKEN bit in the SSI
Control 1 (SSICR1) register. In this mode of operation, SSInCLK from the QSSI master operation
is reflected back as a loopback clock, HSPEEDCLK, to the QSSI module. This allows faster timing
since the logic can can be used to adjust clock to external data relationships. HSPEEDCLK captures
RX data in a separate register . This allows the time between the clock as seen by a remote device
and the internal clock to match more closely.
Receive data is captured in a separate register sampled on loop-back clock (HSPEEDCLK) and the
RX FIFO write control registered on HSPEEDCLK. If the HSCKEN = 1, the corresponding shift register
and FIFO write enable will be selected for use. This supports faster QSSI master speed.
Note: For proper functionality of high speed mode, the HSCLKEN bit in the SSICR1 register should
be set before any SSI data transfer or after applying a reset to the QSSI module. In addition,
the SSE bit must be set to 0x1 before the HSCLKEN bit is set.
20.3.6 Interrupts
The QSSI can generate interrupts when the following conditions are observed:
■ Transmit FIFO service (when the transmit FIFO is half full or less)
■ Receive FIFO service (when the receive FIFO is half full or more)
■ Receive FIFO time-out
■ Receive FIFO overrun
■ End of transmission
■ Receive DMA transfer complete
■ Transmit DMA transfer complete
All of the interrupt events are ORed together before being sent to the interrupt controller, so the
QSSI generates a single interrupt request to the controller regardless of the number of active
interrupts. Each of the seven individual maskable interrupts can be masked by clearing the appropriate
bit in the SSI Interrupt Mask (SSIIM) register (see page 1402). Setting the appropriate mask bit
enables the interrupt.
1381December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller