Datasheet

Figure 20-1. QSSI Module with Advanced, Bi-SSI and Quad-SSI Support
Identification Registers
SSIPCellID0
SSIPCellID1
SSIPCellID2
SSIPCellID3
SSIPeriphID0
SSIPeriphID1
SSIPeriphID2
SSIPeriphID3
SSIPeriphID4
SSIPeriphID5
SSIPeriphID6
SSIPeriphID7
Clock Prescaler
SSICPSR
Control/Status
Interrupt Control
SSIDR
TxFIFO
8 x 16
.
.
.
RxFIFO
8 x 16
.
.
.
Transmit/
Receive
Logic
SSInClk
SSInFss
DMA Control
SSIDMACTL
DMA Request
Interrupt
System Clock
SSISR
SSICR1
SSICR0
SSIRIS
SSIMIS
SSIIM
SSIICR
Clock Control
SSICC
SSI Baud Clock
SSInXDAT2
SSInXDAT3
SSInXDAT0/TX
SSInXDAT1/RX
ALTCLK
20.2 Signal Description
The following table lists the external signals of the QSSI module and describes the function of each.
The QSSI signals are alternate functions for some GPIO signals and default to be GPIO signals at
reset. The "Pin Mux/Pin Assignment" column in the following table lists the possible GPIO pin
placements for the QSSI signals. The AFSEL bit in the GPIO Alternate Function Select
(GPIOAFSEL) register (page 801) should be set to choose the QSSI function. The number in
December 13, 20131376
Texas Instruments-Advance Information
Quad Synchronous Serial Interface (QSSI)