Datasheet

channel if a receive error occurs. If the DMAERR bit of the UARTDMACR register is set and a receive
error occurs, the DMA receive requests are automatically disabled. This error condition can be
cleared by clearing the appropriate UART error interrupt.
When the µDMA is finished transferring data to the TX FIFO or from the RX FIFO, a dma_done
signal is sent to the UART to indicate completion. The dma_done status is indicated through the
DMATXRIS and DMARXIS bits of the UARTRIS register. An interrupt can be generated from these
status bits by setting the DMATXIM and/or DMARXIM bits in the UARTIM register.
Note: The DMATXRIS bit can be used to indicate the µDMA's completion of data transfer to the
TX FIFO. To indicate transfer completion from the UART's serializer, the end-of-transmission
bit (EOT bit) should be enabled in the UARTCTL register. An interrupt can be generated on
an end-of-transmission completion by setting the EOTIM bit of the UARTIM register.
See “Micro Direct Memory Access (μDMA)” on page 707 for more details about programming the
μDMA controller.
19.4 Initialization and Configuration
To enable and initialize the UART, the following steps are necessary:
1. Enable the UART module using the RCGCUART register (see page 404).
2. Enable the clock to the appropriate GPIO module via the RCGCGPIO register (see page 398).
To find out which GPIO port to enable, refer to Table 31-5 on page 2087.
3. Set the GPIO AFSEL bits for the appropriate pins (see page 801). To determine which GPIOs to
configure, see Table 31-4 on page 2070.
4. Configure the GPIO current level and/or slew rate as specified for the mode selected (see
page 803 and page 811).
5. Configure the PMCn fields in the GPIOPCTL register to assign the UART signals to the appropriate
pins (see page 818 and Table 31-5 on page 2087).
To use the UART, the peripheral clock must be enabled by setting the appropriate bit in the
RCGCUART register (page 404). In addition, the clock to the appropriate GPIO module must be
enabled via the RCGCGPIO register (page 398) in the System Control module. To find out which
GPIO port to enable, refer to Table 31-5 on page 2087.
This section discusses the steps that are required to use a UART module. For this example, the
UART clock is assumed to be 20 MHz, and the desired UART configuration is:
■ 115200 baud rate
■ Data length of 8 bits
■ One stop bit
■ No parity
■ FIFOs disabled
■ No interrupts
December 13, 20131320
Texas Instruments-Advance Information
Universal Asynchronous Receivers/Transmitters (UARTs)