Datasheet

19.3.6.2 Flow Control
Flow control can be accomplished by either hardware or software. The following sections describe
the different methods.
Hardware Flow Control (RTS/CTS)
Hardware flow control between two devices is accomplished by connecting the UnRTS output to the
Clear-To-Send input on the receiving device, and connecting the Request-To-Send output on the
receiving device to the UnCTS input.
The UnCTS input controls the transmitter. The transmitter may only transmit data when the UnCTS
input is asserted. The UnRTS output signal indicates the state of the receive FIFO. UnCTS remains
asserted until the preprogrammed watermark level is reached, indicating that the Receive FIFO has
no space to store additional characters.
The UARTCTL register bits 15 (CTSEN) and 14 (RTSEN) specify the flow control mode as shown in
Table 19-2 on page 1317.
Table 19-2. Flow Control Mode
DescriptionRTSENCTSEN
RTS and CTS flow control enabled11
Only CTS flow control enabled01
Only RTS flow control enabled10
Both RTS and CTS flow control disabled00
Note that when RTSEN is 1, software cannot modify the UnRTS output value through the UARTCTL
register Request to Send (RTS) bit, and the status of the RTS bit should be ignored.
Software Flow Control (Modem Status Interrupts)
Software flow control between two devices is accomplished by using interrupts to indicate the status
of the UART. Interrupts may be generated for the UnDSR, UnDCD, UnCTS, and UnRI signals using
bits 3:0 of the UARTIM register, respectively. The raw and masked interrupt status may be checked
using the UARTRIS and UARTMIS register. These interrupts may be cleared using the UARTICR
register.
19.3.7 9-Bit UART Mode
The UART provides a 9-bit mode that is enabled with the 9BITEN bit in the UART9BITADDR
register. This feature is useful in a multi-drop configuration of the UART where a single master
connected to multiple slaves can communicate with a particular slave through its address or set of
addresses along with a qualifier for an address byte. All the slaves check for the address qualifier
in the place of the parity bit and, if set, then compare the byte received with the preprogrammed
address. If the address matches, then it receives or sends further data. If the address does not
match, it drops the address byte and any subsequent data bytes. If the UART is in 9-bit mode, then
the receiver operates with no parity mode. The address can be predefined to match with the received
byte and it can be configured with the UART9BITADDR register. The matching can be extended
to a set of addresses using the address mask in the UART9BITAMASK register. By default, the
UART9BITAMASK is 0xFF, meaning that only the specified address is matched.
When not finding a match, the rest of the data bytes with the 9th bit cleared are dropped. If a match
is found, then an interrupt is generated to the NVIC for further action. The subsequent data bytes
with the cleared 9th bit are stored in the FIFO. Software can mask this interrupt in case μDMA and/or
FIFO operations are enabled for this instance and processor intervention is not required. All the
1317December 13, 2013
Texas Instruments-Advance Information
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TM4C129XNCZAD Microcontroller