Datasheet

receive operations. Note that the state of the HSE bit has no effect on clock generation in ISO 7816
smart card mode (when the SMART bit in the UARTCTL register is set).
Along with the UART Line Control, High Byte (UARTLCRH) register (see page 1335), the UARTIBRD
and UARTFBRD registers form an internal 30-bit register. This internal register is only updated
when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must
be followed by a write to the UARTLCRH register for the changes to take effect.
To update the baud-rate registers, there are four possible sequences:
■ UARTIBRD write, UARTFBRD write, and UARTLCRH write
■ UARTFBRD write, UARTIBRD write, and UARTLCRH write
■ UARTIBRD write and UARTLCRH write
■ UARTFBRD write and UARTLCRH write
19.3.3 Data Transmission
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra
four bits per character for status information. For transmission, data is written into the transmit FIFO.
If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated
in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit
FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 1329) is asserted as soon as
data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while
data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the
last character has been transmitted from the shift register, including the stop bits. The UART can
indicate that it is busy even though the UART may no longer be enabled.
When the receiver is idle (the UnRx signal is continuously 1), and the data input goes Low (a start
bit has been received), the receive counter begins running and data is sampled on the eighth cycle
of Baud16 or fourth cycle of Baud8 depending on the setting of the HSE bit (bit 5) in UARTCTL
(described in “Transmit/Receive Logic” on page 1313).
The start bit is valid and recognized if the UnRx signal is still low on the eighth cycle of Baud16 (HSE
clear) or the fourth cycle of Baud 8 (HSE set), otherwise it is ignored. After a valid start bit is detected,
successive data bits are sampled on every 16th cycle of Baud16 or 8th cycle of Baud8 (that is, one
bit period later) according to the programmed length of the data characters and value of the HSE
bit in UARTCTL. The parity bit is then checked if parity mode is enabled. Data length and parity are
defined in the UARTLCRH register.
Lastly, a valid stop bit is confirmed if the UnRx signal is High, otherwise a framing error has occurred.
When a full word is received, the data is stored in the receive FIFO along with any error bits
associated with that word.
19.3.4 Serial IR (SIR)
The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block
provides functionality that converts between an asynchronous UART data stream and a half-duplex
serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to
provide a digital encoded output and decoded input to the UART. When enabled, the SIR block
uses the UnTx and UnRx pins for the SIR protocol. These signals should be connected to an infrared
transceiver to implement an IrDA SIR physical layer link. The SIR block can receive and transmit,
but it is only half-duplex so it cannot do both at the same time. Transmission must be stopped before
December 13, 20131314
Texas Instruments-Advance Information
Universal Asynchronous Receivers/Transmitters (UARTs)