Datasheet
Register 37: ADC Sample Sequence Extended Input Multiplexer Select 1
(ADCSSEMUX1), offset 0x078
Register 38: ADC Sample Sequence Extended Input Multiplexer Select 2
(ADCSSEMUX2), offset 0x098
This register, along with the ADCSSMUX1 or ADCSSMUX2 register, defines the analog input
configuration for each sample in a sequence executed with either Sample Sequencer 1 or 2. If a bit
in this register is set, the corresponding MUXn field in the ADCSSMUX1 or ADCSSMUX2 register
selects from AIN[23:16]. When a bit in this register is clear, the corresponding MUXn field selects
from AIN[15:0]. This register is 16 bits wide and contains information for four possible samples.
The ADCSSEMUX1 register controls Sample Sequencer 1 and the ADCSSEMUX2 register controls
Sample Sequencer 2.
Note that this register is not used when the differential channel designation is used (the Dn bit is set
in the ADCSSCTL1 or ADCSSCTL2 register) because the ADCSSMUX1 or ADCSSMUX2 register
can select all the available pairs.
ADC Sample Sequence Extended Input Multiplexer Select n (ADCSSEMUXn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x078
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
EMUX0reservedEMUX1reservedEMUX2reservedEMUX3reserved
RWRORORORWRORORORWRORORORWROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:13
4th Sample Input Select (Upper Bit)
The EMUX3 field is used during the fourth sample of a sequence executed
with the sample sequencer.
DescriptionValue
The fourth sample input is selected from AIN[15:0] using the
ADCSSMUX1 or ADCSSMUX2 register. For example, if the
MUX3 field is 0x0, AIN0 is selected.
0
The fourth sample input is selected from AIN[23:16] using
the ADCSSMUX1 or ADCSSMUX2 register. For example, if the
MUX3 field is 0x0, AIN16 is selected.
1
0x0RWEMUX312
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved11:9
1285December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller