Datasheet

18.3.2.9 Dither Enable
The ADCCTL register provides a dither enable bit to reduce random noise in ADC sampling. The
DITHER bit is enabled by default at reset. Dither mode can be disabled by clearing the DITHER bit
in the ADDCCTL register.
18.3.3 Hardware Sample Averaging Circuit
Higher precision results can be generated using the hardware averaging circuit, however, the
improved results are at the cost of throughput. Up to 64 samples can be accumulated and averaged
to form a single data entry in the sequencer FIFO. Throughput is decreased proportionally to the
number of samples in the averaging calculation. For example, if the averaging circuit is configured
to average 16 samples, the throughput is decreased by a factor of 16.
By default the averaging circuit is off, and all data from the converter passes through to the sequencer
FIFO. The averaging hardware is controlled by the ADC Sample Averaging Control (ADCSAC)
register (see page 1253). A single averaging circuit has been implemented, thus all input channels
receive the same amount of averaging whether they are single-ended or differential.
Figure 18-6 shows an example in which the ADCSAC register is set to 0x2 for 4x hardware
oversampling and the IE1 bit is set for the sample sequence, resulting in an interrupt after the
second averaged value is stored in the FIFO.
Figure 18-6. Sample Averaging Example
A+B+C+D
4
A+B+C+D
4
INT
18.3.4 Analog-to-Digital Converter
The Analog-to-Digital Converter (ADC) module uses a Successive Approximation Register (SAR)
architecture to deliver a 12-bit, low-power, high-precision conversion value. The successive
approximation uses a switched capacitor array to perform the dual functions of sampling and holding
the signal as well as providing the 12-bit DAC operation.
December 13, 20131210
Texas Instruments-Advance Information
Analog-to-Digital Converter (ADC)