Datasheet
F
CONV
= 1/((N
SH
+ 12)*T
ADC
)
where:
■ N
SH
is the number of ADC conversion clock periods in the sample time
■ T
ADC
is the ADC conversion clock period, which is 1/16 MHz for 1 Msps
These two equations show that when N
SH
is increased, F
CONV
is reduced and R
S
is increased:
Table 18-4. R
S
and F
CONV
Values with Varying N
SH
Values and T
ADC
= 1/16 MHz
25612864321684N
SH
189,85993,68045,59021,5459,5223,511506R
S
(Ω)
601142113645718001000F
CONV
(Ksps)
The system designer must take into consideration both of these factors for optimal ADC operation.
18.3.2.6 Sample Phase Control
The trigger source for ADC0 and ADC1 may be independent or the two ADC modules may operate
from the same trigger source and operate on the same or different inputs. If the converters are
running at the same sample rate, they may be configured to start the conversions coincidentally or
one ADC may be programmed to lag up to 15 clock cycles relative to the other ADC. The sample
time can be delayed from the standard sampling time by programming the PHASE field in the ADC
Sample Phase Control (ADCSPC) register. Figure 18-3 on page 1207 shows an example of various
phase relationships at a 1 Msps rate.
Figure 18-3. ADC Sample Phases
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
ADC Sample Clock
PHASE 0x0 (no lag)
PHASE 0x1 (1 ADC clock lag)
PHASE 0xE (14 ADC clock lag)
PHASE 0xF (15 ADC clock lag)
.
.
.
.
.
.
.
.
.
.
.
.
19
This feature can be used to double the sampling rate of an input. Both ADC Module 0 and ADC
Module 1 can be programmed to sample the same input. ADC module 0 can sample at the standard
position (the PHASE field in the ADCSPC register is 0x0). ADC Module 1 can be configured to sample
with a phase lag (PHASE is nonzero). For a sample rate of samples/second at , the TSHn field of all
of the sequencer samples of both ADCs must be programmed to 0x0 and the PHASE field of one of
the ADC modules must be set to 0x8. The two modules can be be synchronized using the GSYNC
and SYNCWAIT bits in the ADC Processor Sample Sequence Initiate (ADCPSSI) register. Software
can then combine the results from the two modules to create a sample rate of one million
samples/second at 16MHz as shown in Figure 18-4 on page 1208.
1207December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller