Datasheet

PWM generator, and continuous sampling. The processor triggers sampling by setting the SSx bits
in the ADC Processor Sample Sequence Initiate (ADCPSSI) register.
Care must be taken when using the continuous sampling trigger. If a sequencer's priority is too high,
it is possible to starve other lower priority sequencers. Generally, a sample sequencer using
continuous sampling should be set to the lowest priority. Continuous sampling can be used with a
digital comparator to cause an interrupt when a particular voltage is seen on an input.
18.3.2.5 Sample and Hold Window Control
The ADC module provides the capability of programming the sample and hold window of each step
in a sequence through the ADC Sample Sequence n Sample and Hold Time (ADCSSTSHn)
register. Each TSHn field can be written with a different sample and hold width, which is represented
in ADC clocks. The table below gives the allowed encodings:
Table 18-3. Sample and Hold Width in ADC Clocks
N
SH
TSHn Encoding
40x0
reserved0x1
80x2
reserved0x3
160x4
reserved0x5
320x6
reserved0x7
640x8
reserved0x9
1280xA
reserved0xB
2560xC
reserved0xD-0xF
Since both source resistance and conversion frequency are functions of the sample and hold number
(N
SH
), the system designer must evaluate how changing this value can effect system performance.
Source resistance can be calculated by the following equation:
R
S
= ((N
SH
* T
ADC
)/C
ADC
* ln(2
N
)) - R
ADC
where:
■ N
SH
is the number of ADC conversion clock periods in the sample time
■ T
ADC
is the ADC conversion clock period, which is 1/16 MHz for 1 Msps
■ C
ADC
is the ADC equivalent input capacitance, which equals 10 pF
■ N is the resolution which is 12-bits
■ R
ADC
is the ADC equivalent input resistance which is 2.5 kΩ
Conversion frequency can be calculated using the following equation:
December 13, 20131206
Texas Instruments-Advance Information
Analog-to-Digital Converter (ADC)