Datasheet

DescriptionResetTypeNameBit/Field
GPTM Timer B Interval Load Write
DescriptionValue
Update the GPTMTBR and GPTMTBV registers with the value
in the GPTMTBILR register on the next cycle. Also update the
GPTMTBPS register with the value in the GPTMTBPR register
on the next cycle.
0
Update the GPTMTBR and GPTMTBV registers with the value
in the GPTMTBILR register on the next timeout. Also update
the GPTMTBPS register with the value in the GPTMTBPR
register on the next timeout.
1
Note the state of this bit has no effect when counting up.
The bit descriptions above apply if the timer is enabled and running. If
the timer is disabled (TBEN is clear) when this bit is set, GPTMTBR,
GPTMTBV and are updated when the timer is enabled. If the timer is
stalled (TBSTALL is set), GPTMTBR and GPTMTBPS are updated
according to the configuration of this bit.
0RWTBILD8
GPTM Timer B Snap-Shot Mode
DescriptionValue
Snap-shot mode is disabled.0
If Timer B is configured in the periodic mode, the actual
free-running value of Timer B is loaded at the time-out event
into the GPTM Timer B (GPTMTBR) register. If the timer
prescaler is used, the prescaler snapshot is loaded into the
GPTM Timer B (GPTMTBPR).
1
0RWTBSNAPS7
GPTM Timer B Wait-on-Trigger
DescriptionValue
Timer B begins counting as soon as it is enabled.0
If Timer B is enabled (TBEN is set in the GPTMCTL register),
Timer B does not begin counting until it receives a trigger from
the timer in the previous position in the daisy chain, see . This
function is valid for one-shot, periodic, and PWM modes.
1
0RWTBWOT6
GPTM Timer B Match Interrupt Enable
DescriptionValue
The match interrupt is disabled for match events. Additionally,
triggers to the DMA and ADC on match events are prevented.
0
An interrupt is generated when the match value in the
GPTMTBMATCHR register is reached in the one-shot and
periodic modes.
1
0RWTBMIE5
1131December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller