Datasheet

DescriptionResetTypeNameBit/Field
GPTM Timer A Interval Load Write
DescriptionValue
Update the GPTMTAR and GPTMTAV registers with the value
in the GPTMTAILR register on the next cycle. Also update the
GPTMTAPS register with the value in the GPTMTAPR register
on the next cycle.
0
Update the GPTMTAR and GPTMTAV registers with the value
in the GPTMTAILR register on the next timeout. Also update
the GPTMTAPS register with the value in the GPTMTAPR
register on the next timeout.
1
Note the state of this bit has no effect when counting up.
The bit descriptions above apply if the timer is enabled and running. If
the timer is disabled (TAEN is clear) when this bit is set, GPTMTAR
GPTMTAV and GPTMTAPs, are updated when the timer is enabled. If
the timer is stalled (TASTALL is set), GPTMTAR and GPTMTAPS are
updated according to the configuration of this bit.
0RWTAILD8
GPTM Timer A Snap-Shot Mode
DescriptionValue
Snap-shot mode is disabled.0
If Timer A is configured in the periodic mode, the actual
free-running, capture or snapshot value of Timer A is loaded at
the time-out event/capture or snapshot event into the GPTM
Timer A (GPTMTAR) register. If the timer prescaler is used,
the prescaler snapshot is loaded into the GPTM Timer A
(GPTMTAPR).
1
0RWTASNAPS7
GPTM Timer A Wait-on-Trigger
Note: If the application requires cyclical daisy-chaining, the TAWOT
bit in the GPTMTAMR register of Timer 0 can be set. In this
case, Timer 0 waits for a trigger from the last timer module in
the chain.
DescriptionValue
Timer A begins counting as soon as it is enabled.0
If Timer A is enabled (TAEN is set in the GPTMCTL register),
Timer A does not begin counting until it receives a trigger from
the timer in the previous position in the daisy chain, see Figure
16-8 on page 1117. This function is valid for one-shot, periodic,
and PWM modes.
1
0RWTAWOT6
GPTM Timer A Match Interrupt Enable
DescriptionValue
The match interrupt is disabled for match events. Additionally,
triggers to the DMA and ADC on match events are prevented.
0
An interrupt is generated when the match value in the
GPTMTAMATCHR register is reached in the one-shot and
periodic modes.
1
0RWTAMIE5
1127December 13, 2013
Texas Instruments-Advance Information
Tiva
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TM4C129XNCZAD Microcontroller