Datasheet

configuring and enabling the appropriate μDMA channel as well as the type of trigger enable in the
GPTM DMA Event (GPTMDMAEV) register. See “Channel Configuration” on page 712.
After the match value is reached in down-count mode, the counter is then reloaded using the value
in GPTMTnILR and GPTMTnPR registers, and stopped because the GPTM automatically clears
the TnEN bit in the GPTMCTL register. Once the event count has been reached, all further events
are ignored until TnEN is re-enabled by software. In up-count mode, the timer is reloaded with 0x0
and continues counting.
Figure 16-2 on page 1111 shows how Input Edge-Count mode works. In this case, the timer start
value is set to GPTMTnILR =0x000A and the match value is set to GPTMTnMATCHR =0x0006 so
that four edge events are counted. The counter is configured to detect both edges of the input signal.
Note that the last two edges are not counted because the timer automatically clears the TnEN bit
after the current count matches the value in the GPTMTnMATCHR register.
Figure 16-2. Input Edge-Count Mode Example, Counting Down
Input Signal
Timer stops,
flags
asserted
Timer reload
on next cycle
Ignored Ignored
Count
0x000A
0x0006
0x0007
0x0008
0x0009
16.3.3.4 Input Edge-Time Mode
Note: For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
In Edge-Time mode, the timer is configured as a 24-bit up- or down-counter including the optional
prescaler with the upper timer value stored in the GPTMTnPR register and the lower bits in the
GPTMTnILR register. In this mode, the timer is initialized to the value loaded in the GPTMTnILR
and GPTMTnPR registers when counting down and 0x0 when counting up. The timer is capable of
capturing three types of events: rising edge, falling edge, or both. The timer is placed into Edge-Time
mode by setting the TnCMR bit in the GPTMTnMR register, and the type of event that the timer
captures is determined by the TnEVENT fields of the GPTMCTL register. Table 16-8 on page 1112
shows the values that are loaded into the timer registers when the timer is enabled.
1111December 13, 2013
Texas Instruments-Advance Information
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TM4C129XNCZAD Microcontroller