Datasheet

When software writes the TAEN bit in the GPTMCTL register, the counter starts counting up from
its preloaded value of 0x1. When the current count value matches the preloaded value in the
GPTMTnMATCHR registers, the GPTM asserts the RTCRIS bit in GPTMRIS and continues counting
until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When the timer
value reaches the terminal count, the timer rolls over and continues counting up from 0x0. If the
RTC interrupt is enabled in GPTMIMR, the GPTM also sets the RTCMIS bit in GPTMMIS and
generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR.
In this mode, the GPTMTnR and GPTMTnV registers always have the same value.
In addition to generating interrupts, the RTC can generate a μDMA trigger. The μDMA trigger is
enabled by configuring and enabling the appropriate μDMA channel as well as the type of trigger
enable in the GPTM DMA Event (GPTMDMAEV) register. See “Channel Configuration” on page 712.
16.3.3.3 Input Edge-Count Mode
Note: For rising-edge detection, the input signal must be High for at least two clock periods
following the rising edge. Similarly, for falling-edge detection, the input signal must be Low
for at least two clock periods following the falling edge. Based on this criteria, the maximum
input frequency for edge detection is 1/4 of the frequency.
In Edge-Count mode, the timer is configured as a 24-bit up- or down-counter including the optional
prescaler with the upper count value stored in the GPTM Timer n Prescale (GPTMTnPR) register
and the lower bits in the GPTMTnR register. In this mode, the timer is capable of capturing three
types of events: rising edge, falling edge, or both. To place the timer in Edge-Count mode, the
TnCMR bit of the GPTMTnMR register must be cleared. The type of edge that the timer counts is
determined by the TnEVENT fields of the GPTMCTL register. During initialization in down-count
mode, the GPTMTnMATCHR and GPTMTnPMR registers are configured so that the difference
between the value in the GPTMTnILR and GPTMTnPR registers and the GPTMTnMATCHR and
GPTMTnPMR registers equals the number of edge events that must be counted. In up-count mode,
the timer counts from 0x0 to the value in the GPTMTnMATCHR and GPTMTnPMR registers. Note
that when executing an up-count, that the value of GPTMTnPR and GPTMTnILR must be greater
than the value of GPTMTnPMR and GPTMTnMATCHR. Table 16-7 on page 1110 shows the values
that are loaded into the timer registers when the timer is enabled.
Table 16-7. Counter Values When the Timer is Enabled in Input Edge-Count Mode
Count Up ModeCount Down ModeRegister
0x0GPTMTnPR in combination with GPTMTnILRGPTMTnR
0x0GPTMTnPR in combination with GPTMTnILRGPTMTnV
When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled
for event capture. Each input event on the CCP pin decrements or increments the counter by 1 until
the event count matches GPTMTnMATCHR and GPTMTnPMR. When the counts match, the GPTM
asserts the CnMRIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register, and holds it until
it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register. If the capture mode match
interrupt is enabled in the GPTM Interrupt Mask (GPTMIMR) register, the GPTM also sets the
CnMMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register. In up-count mode, the
current count of the input events is held in both the GPTMTnR and GPTMTnV registers. In
down-count mode, the current count of the input events can be obtained by subtracting the GPTMTnR
or GPTMTnV from the value made up of the GPTMTnPR and GPTMTnILR register combination.
In addition to generating interrupts, an ADC and/or a μDMA trigger can be generated. The ADC
trigger is enabled by setting the TnOTE bit in GPTMCTL and the event that activates the ADC is
configured in the GPTM ADC Event (GPTMADCEV) register. The μDMA trigger is enabled by
December 13, 20131110
Texas Instruments-Advance Information
General-Purpose Timers