Datasheet

Table 16-5. 16-Bit Timer With Prescaler Configurations
UnitsMax Time# of Timer Clocks (Tc)
a
Prescale (8-bit value)
msPending100000000
msPending200000001
msPending300000010
------------------
msPending25411111101
msPending25511111110
msPending25611111111
a. Tc is the clock period.
Timer Compare Action Mode
The timer compare mode is an extension to the GPTM's existing one-shot and periodic modes. This
mode can be used when an application requires a pin change state at some time in the future,
regardless of the processor state. The compare mode does not operate when the PWM mode is
active and is mutually exclusive to the PWM mode. The compare mode is enabled when the TAMR
field is set to 0x1 or 0x2 (one-shot or periodic), the TnAMS bit is 0 (capture or compare mode) and
the TCACT field is nonzero in the GPTM Timer n Mode (GPTMTnMR) register. Depending on the
TCACT encoding, the timer can perform a set, clear or toggle on the corresponding CCPn pin when
a timer match occurs. In 16-bit mode, the corresponding CCP pin can have an action applied, but
when operating in 32-bit mode, the action can only be applied to the even CCP pin.
The TCACT field can be changed while the GPTM is enabled to generate different combinations of
actions. For example, during a periodic event, encodings TCACT = 0x6 or 0x7 can be used to force
the initial state of the CCPn pin before the first interrupt and following that, TCACT=0x2 and TCACT=0x3
can be used (alternately) to change the sense of the pin for the subsequent toggle, while possible
changing load value for the next period.
The time-out interrupts used for one-shot and periodic modes are used in the compare action modes.
Thus, the TnTORIS bits in the GPTMRIS register are triggered if the appropriate mask bits are set
in the GPTMIM register.
16.3.3.2 Real-Time Clock Timer Mode
In Real-Time Clock (RTC) mode, the concatenated versions of the Timer A and Timer B registers
are configured as an up-counter. When RTC mode is selected for the first time after reset, the
counter is loaded with a value of 0x1. All subsequent load values must be written to the GPTM
Timer n Interval Load (GPTMTnILR) registers (see page 1151). If the GPTMTnILR register is loaded
with a new value, the counter begins counting at that value and rolls over at the fixed value of
0xFFFFFFFF. Table 16-6 on page 1109 shows the values that are loaded into the timer registers when
the timer is enabled.
Table 16-6. Counter Values When the Timer is Enabled in RTC Mode
Count Up ModeCount Down ModeRegister
0x1Not availableGPTMTnR
0x1Not availableGPTMTnV
Not availableNot availableGPTMTnPS
The input clock on a CCP0 input is required to be 32.768 KHz in RTC mode. The clock signal is
then divided down to a 1-Hz rate and is passed along to the input of the counter.
1109December 13, 2013
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TM4C129XNCZAD Microcontroller